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m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers description these are single-chip 16-bit microcomputers designed with high-per- formance cmos silicon gate technology, being packaged in 64-pin plastic molded qfp or shrink plastic molded sdip. these microcom- puters support the 7900 series instruction set, which are enhanced and expanded instruction set and are upper-compatible with the 7700/7751 series instruction set. the cpu of these microcomputers is a 16-bit parallel processor that can also be switched to perform 8-bit parallel processing. also, the bus interface unit of these microcomputers enhances the memory access efficiency to execute instructions fast. therefore, these mi- crocomputers are suitable for office, business, and industrial equip- ment controller that require high-speed processing of large data. also, they are suitable for motor-control equipment since each of them includes the motor control circuit. distinctive features number of basic machine instructions .................................... 203 memory [m37905m4c-xxxfp, m37905m4c-xxxsp] rom .............................................................................. 32 kbytes ram ............................................................................. 1024 bytes [m37905m6c-xxxfp, M37905M6C-XXXSP] rom .............................................................................. 48 kbytes ram ............................................................................. 3072 bytes [m37905m8c-xxxfp, m37905m8c-xxxsp] rom .............................................................................. 60 kbytes ram ............................................................................. 3072 bytes instruction execution time the fastest instruction at 20 mhz frequency ........................ 50 ns single power supply .................................................... 5 v ?0.5 v interrupts ........... 8 external sources, 23 internal sources, 7 levels multi-functional 16-bit timer ................................................. 10 + 3 (three-phase motor drive waveform and pulse motor drive wave- form output are available.) serial i/o (uart or clock synchronous) ..................................... 3 10-bit a-d converter .......................................... 12-channel inputs 8-bit d-a converter ............................................ 2-channel outputs 12-bit watchdog timer programmable input/output (ports p1, p2, p4, p5, p6, p7, p8) .. 50 application control devices for office equipment such as copiers and facsimiles control devices for industrial equipment such as communication and measuring instruments control devices for equipment, requiring motor control, such as inverter air conditioners and general-purpose inverters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 22 21 20 19 18 17 p7 3 /an 3 p7 2 /an 2 p7 1 /an 1 p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 p6 3 /ta1 in /w/rtp0 3 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw p6out cut /int 4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 34 33 32 31 30 29 28 27 26 25 24 23 p7 0 /an 0 p6 7 /ta3 in /rtp1 3 p6 6 /ta3 out /rtp1 2 md0 reset x in x out v cont v ss p5 3 /int 3 /rtp trg0 p5 2 /int 2 /rtp trg1 p5 1 /int 1 p4out cut /int 0 p4 7 /ta8 in /rtp3 3 p4 6 /ta8 out /rtp3 2 p4 5 /ta7 in /rtp3 1 p4 4 /ta7 out /rtp3 0 p4 3 /ta6 in /rtp2 3 p4 2 /ta6 out /rtp2 2 p2 3 /ta9 in p2 2 /ta9 out p2 1 /ta4 in p2 0 /ta4 out p1 7 /txd 1 p1 6 /rxd 1 p1 5 /cts 1 /clk 1 p1 4 /cts 1 /rts 1 p1 3 /txd 0 p8 3 /an 11 /t x d 2 p8 2 /an 10 /r x d 2 p8 1 /an 9 /cts 2 /clk 2 v cc av cc v ref av ss v ss p7 7 /an 7 /da 0 p7 6 /an 6 p7 5 /an 5 p7 4 /an 4 p8 0 /an 8 /cts 2 /rts 2 /da 1 m37905m x c-xxxfp p1 1 /cts 0 /clk 0 p1 0 /cts 0 /rts 0 p4 1 /ta5 in /rtp2 1 p4 0 /ta5 out /rtp2 0 md1 p2 7 p2 6 (/tb2 in ) p2 5 (/tb1 in ) p2 4 (/tb0 in ) p1 2 /r x d 0 note note m37905mxc-xxxfp pin configuration (top view) outline 64p6n-a note : allocation of pins tb0 in to tb2 in can be switched by software.
m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 2 m37905mxc-xxxsp pin configuration (top view) outline 64p4b 63 64 2 1 p7 5 /an 5 p7 6 /an 6 p7 7 /an 7 / da 0 p8 0 /an 8 / cts 2 /rts 2 / da 1 p8 2 /an 10 /rxd 2 p8 1 /an 9 /cts 2 /clk 2 p1 0 /cts 0 /rts 0 p1 1 /cts 0 /clk 0 p1 4 /cts 1 /rts 1 p2 0 /ta4 out p2 1 /ta4 in p2 2 /ta9 out p2 3 /ta9 in p2 5 (/tb1 in ) p2 6 (/tb2 in ) p2 7 md1 v ss p2 4 (/tb0 in ) p1 5 /cts 1 /clk 1 p1 6 /rxd 1 av cc p1 2 /rxd 0 p1 3 /txd 0 p1 7 /txd 1 62 44 45 46 47 48 49 50 51 52 53 54 56 57 58 59 60 61 55 3 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 10 v ref p6 5 /ta2 in /u/rtp1 1 p6 4 /ta2 out /v/rtp1 0 p6 3 /ta1 in /w/rtp0 3 m37905m x c-xxxsp 32 31 30 29 28 27 26 25 24 23 22 p6 2 /ta1 out /u/rtp0 2 p6 1 /ta0 in /v/rtp0 1 p6 0 /ta0 out /w/rtp0 0 p5 7 /int 7 /tb2 in /idu p5 6 /int 6 /tb1 in /idv p5 5 /int 5 /tb0 in /idw md0 v cont reset p6out cut /int 4 v ss p4 0 /ta5 out /rtp2 0 p4 1 /ta5 in /rtp2 1 p4 2 /ta6 out /rtp2 2 p4 4 /ta7 out /rtp3 0 p4 5 /ta7 in /rtp3 1 p4 6 /ta8 out /rtp3 2 p4 3 /ta6 in /rtp2 3 33 34 35 36 37 38 39 40 41 42 43 p8 3 /an 11 /txd 2 p7 3 /an 3 p7 4 /an 4 p7 1 /an 1 p7 2 /an 2 p7 0 /an 0 p6 7 /ta3 in /rtp1 3 p6 6 /ta3 out /rtp1 2 x in x out p5 3 /int 3 /rtp trg0 p5 2 /int 2 /rtp trg1 v cc av ss p4 7 /ta8 in /rtp3 3 p4out cut /int 0 p5 1 /int 1 note note note : allocation of pins tb0 in to tb2 in can be switched by software. outline 64p4b
3 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers block diagram central processing unit (cpu) bus interface unit (biu) reset md1 v reference voltage input instruction register (8) ref (0v) av ss av cc v cc x clock input clock generating circuit reset input clock output in x out address bus data bus (odd) data bus (even) a-d converter (12) uart1 (9) uart0 (9) watchdog timer timer tb1 (16) timer tb2 (16) timer tb0 (16) d-a 1 converter (8) timer ta1 (16) timer ta2 (16) timer ta3 (16) timer ta4 (16) timer ta0 (16) ram (note) p6(8) input/output p6 p5(6) input/output p5 p7(8) input/output p7 p4(8) input/output p4 d-a 0 converter (8) p8(4) input/output p8 md0 (0v) v ss p4out cut rom (note) v cont timer ta6 (16) timer ta7 (16) timer ta8 (16) timer ta9 (16) timer ta5 (16) p6out cut p2(8) input/output p2 p1(8) input/output p1 uart2 (9) m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp rom 32 kbytes 48 kbytes 60 kbytes ram 1 kbyte 3 kbytes 3 kbytes note: data buffer dq 0 (8) data buffer dq 1 (8) data buffer dq 2 (8) data buffer dq 3 (8) instruction queue buffer q 0 (8) instruction queue buffer q 1 (8) instruction queue buffer q 2 (8) instruction queue buffer q 3 (8) instruction queue buffer q 4 (8) instruction queue buffer q 5 (8) instruction queue buffer q 6 (8) instruction queue buffer q 7 (8) instruction queue buffer q 8 (8) instruction queue buffer q 9 (8) program address register pa (24) data address register da (24) incrementer (24) incrementer/decrementer (24) input buffer register ib (16) program counter pc (16) program bank register pg (8) processor status register ps (11) direct page register dpr0 (16) direct page register dpr1 (16) direct page register dpr2 (16) direct page register dpr3 (16) stack pointer s (16) index register y (16) index register x (16) accumulator b (16) accumulator a (16) arithmetic logic unit (16) data bank register dt (8)
m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 4 memory expansion operating ambient temperature range device structure package ports?input/output characteristics power supply voltage power dissipation number of basic machine instructions instruction execution time external clock input frequency f(x in ) system clock frequency f(f sys ) memory size programmable input/output ports multi-functional timers serial i/o a-d converter d-a converter dead-time timer watchdog timer interrupts clock generating circuit pll frequency multiplier rom ram p1, p2, p4, p6, p7 p5 p8 ta0?a9 tb0?b2 uart0, uart1, and uart2 functions functions parameter nput/output withstand voltage utput current maskable interrups non-maskable interrups 203 50 ns (the fastest instruction at f(f sys ) = 20 mhz) 20 mhz (max.) 20 mhz (max.) (note 1) (note 1) 8-bit ? 5 6-bit ? 1 4-bit ? 1 16-bit ? 10 16-bit ? 3 (uart or clock synchronous serial i/o) ? 3 10-bit successive approximation method ? 1 (12 channels) 8-bit ? 2 8-bit ? 3 12-bit ? 1 8 external sources, 20 internal sources. each interrupt can be set to a priority level within the range of 0? by software. 3 internal sources incorporated (externally connected to a ceramic resonator or quartz-crystal resonator). the following multiplication ratios are available: ? 2, ? 3, ? 4. 5 v?.5 v 125 mw (at f(f sys ) = 20 mhz, typ, ; the pll frequency multiplier is inactive.) 5 v 5 ma not available (single-chip mode only). ?0 to 85 ? cmos high-performance silicon gate process (note 2) 2: packages m37905m4c-xxxfp, m37905m6c-xxxfp, m37905m8c-xxxfp 64-pin plastic molded qfp (64p6n-a) m37905m4c-xxxsp, M37905M6C-XXXSP, m37905m8c-xxxsp 64-pin shrink plastic moldeds dip (64p4b) m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp rom ram 32 kbytes 48 kbytes 60 kbytes 1024 bytes 3072 bytes 3072 bytes notes 1:
5 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers vcc, vss md0 md1 reset x in x out v cont avcc, avss v ref p1 0 ?1 7 p2 0 ?2 7 p4 0 ?4 7 p5 1 ?5 3, p5 5 ?5 7 p6 0 ?6 7 p7 0 ?7 7 p8 0 ?8 3 p4out cut p6out cut power supply input md0 md1 reset input clock input clock output filter circuit connection analog power supply input reference voltage input i/o port p1 i/o port p2 i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 p4out cut input p6out cut input input input input input output input i/o i/o i/o i/o i/o i/o i/o input input apply 5 v?.5 v to vcc, and 0 v to vss. connect this pin to v ss . connect this pin to vss. the microcomputer is reset when ??level is applies to this pin. these are input and output pins of the internal clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between pins x in and x out . when an external clock is used, the clock source should be connected to pin x in , and pin x out should be left open. when using the pll frequency multiplier, connect this pin to the filter circuit. when not using the pll frequency multiplier, this pin should be left open. power supply input pins for the a-d and d-a converters. connect avcc to vcc, and avss to vss externally. this is the reference voltage input pin for the a-d and d-a converters. port p1 is an 8-bit i/o port. this port has an i/o direction register, and each pin can be programmed for input or output. these pins enter the input mode ar reset. these pins also function as i/o pins of uart0, 1. in addition to having the same functions as port p1, these pins function as i/o pins for timers a4 and a9. also, they can be programmed to function as input pins for tim- ers b0 to b2. in addition to having the same functions as port p1, these pins function as i/o pins for timers a5 to a8. also, they function as output pins for motor drive waveform. in addition to having the same functions as port p1, these pins function as input pins for int 1 to int 3 and int 5 to int 7 . also, pins p5 5 to p5 7 function as input pins for timers b0 to b2 and as input pins for position data in the three-phase waveform mode; and pins p5 2 and p5 3 function as trigger-input pins in the pulse output port mode. in addition to having the same functions as port p1, these pins function as i/o pins for timers a0 to a3. also, they function as motor drive waveform output pins. in addition to having the same functions as port p1, these pins function as input pins for the a-d converter. also, p7 7 functions as an output pin for the d-a converter. in addition to having the same functions as port p1, these pins function as input pins for the a-d converter. also, these pins function as i/o pins for uart2,and pin p8 0 functions as an output pin for the d-a converter. this pin has the function to forcibly place port p4 pins in the input mode. also, this pin functions as an input pin for int 0 ; and this pin is used to input a signal, which forcibly cuts off a motor drive waveform output. this pin has the function to forcibly place port p6 pins in the input mode. also, this pin functions as an input pin for int 4 ; and this pin is used to input a signal, which forcibly cuts off a motor drive waveform output. pin description functions input/ output name pin
m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 6 fig. 1 (1) memory map of m37905m4c-xxxfp/sp (single-chip mode) basic function blocks these microcomputers contain the following devices in the single chip: rom, ram, cpu, bus interface unit, and peripheral devices such as the interrupt control circuit, timers, serial i/o, a-d converter, d-a converter, i/o ports, clock generating circuit, etc. memory figures 1 (1) through (3) show the memory maps. the address space is 64 kbytes from addresses 0 16 through ffff 16 . this ad- dress space is called bank 0 16 . the internal rom and ram are allocated as shown in figures 1 (1) through (3). addresses ffb4 16 through ffff 16 contain the reset and the in- terrupt vector addresses, and the interrupt vectors are stored there. for details, refer to the section on interrupts. allocated to addresses 0 16 through ff 16 are peripheral devices such as i/o ports, a-d converter, d-a converter, serial i/o, timers, interrupt control registers, etc. figures 2 and 3 show the location of sfrs. int 4 a-d conversion reserved area reserved area address matching detect reserved area int 5 int 6 int 7 timer a5 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 received area reset dbc 000000 16 bank 0 16 00ffff 16 000000 16 000c00 16 0000ff 16 00fffe 16 00ffb4 16 internal ram 1024 bytes internal rom 32 kbytes peripheral devices' control registers 000fff 16 001000 16 000bff 16 unused area unused area 007fff 16 008000 16 00ffb4 16 00ffff 16 timer a6 timer a7 timer a8 timer a9 uart2 receive uart2 transmit 000000 16 0000ff 16 peripheral devices' control registers (see figures 2 and 3.) 000100 16
7 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 1 (2) memory map of m37905m6c-xxxfp/sp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area int 5 int 6 int 7 timer a5 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 int 2 int 1 int 0 reserved area reset dbc 000000 16 bank 0 16 00ffff 16 000000 16 000400 16 0000ff 16 00fffe 16 00ffb4 16 internal ram 3072 bytes internal rom 48 kbytes peripheral devices' control registers 000fff 16 001000 16 0003ff 16 unused area unused area 003fff 16 004000 16 00ffb4 16 00ffff 16 timer a6 timer a7 timer a8 timer a9 uart2 receive uart2 transmit 000000 16 0000ff 16 peripheral devices' control registers (see figures 2 and 3.) 000100 16
m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 8 fig. 1 (3) memory map of m37905m8c-xxxfp/sp (single-chip mode) int 4 a-d conversion reserved area reserved area address matching detect reserved area int 5 int 6 int 7 timer a5 uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 interrupt vector table timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer brk instruction zero divide int 3 reserved area reset dbc 000000 16 bank 0 16 00ffff 16 000000 16 000400 16 0000ff 16 00fffe 16 00ffb4 16 internal ram 3072 bytes internal rom 60 kbytes peripheral devices' control registers 000fff 16 001000 16 0003ff 16 unused area 00ffb4 16 00ffff 16 timer a6 timer a7 timer a8 timer a9 uart2 receive uart2 transmit 000000 16 0000ff 16 peripheral devices' control registers (see figures 2 and 3.) 000100 16 int 2 int 1 int 0
9 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 2 location of sfrs (1) 000000 16 000001 16 000002 16 000003 16 000004 16 000005 16 000006 16 000007 16 000008 16 000009 16 00000a 16 00000b 16 00000c 16 00000d 16 00000e 16 00000f 16 000010 16 000011 16 000012 16 000013 16 000014 16 000015 16 000016 16 000017 16 000018 16 000019 16 00001a 16 00001b 16 00001c 16 00001d 16 00001e 16 00001f 16 000020 16 000021 16 000022 16 000023 16 000024 16 000025 16 000026 16 000027 16 000028 16 000029 16 00002a 16 00002b 16 00002c 16 00002d 16 00002e 16 00002f 16 000030 16 000031 16 000032 16 000033 16 000034 16 000035 16 000036 16 000037 16 000038 16 000039 16 00003a 16 00003b 16 00003c 16 00003d 16 00003e 16 00003f 16 port p2 register reserved area (note) port p1 direction register reserved area (note) port p1 register reserved area (note) port p2 direction register reserved area (note) port p4 register port p5 register port p4 direction register port p5 direction register port p6 register port p7 register port p6 direction register port p7 direction register port p8 register port p8 direction register reserved area (note) reserved area (note) reserved area (note) reserved area (note) a-d control register 0 a-d control register 1 a-d register 0 a-d register 1 a-d register 2 a-d register 3 uart0 transmit/receive mode register uart0 band rate register (brg0) uart0 transmit buffer register uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart0 receive buffer register uart1 transmit/receive mode register uart1 baud rate register (brg1) uart1 transmit buffer register uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart1 receive buffer register address (hexadecimel notation) address (hexadecimel notation) 000040 16 000041 16 000042 16 000043 16 000044 16 000045 16 000046 16 000047 16 000048 16 000049 16 00004a 16 00004b 16 00004c 16 00004d 16 00004e 16 00004f 16 000050 16 000051 16 000052 16 000053 16 000054 16 000055 16 000056 16 000057 16 000058 16 000059 16 00005a 16 00005b 16 00005c 16 00005d 16 00005e 16 00005f 16 000060 16 000061 16 000062 16 000063 16 000064 16 000065 16 000066 16 000067 16 000068 16 000069 16 00006a 16 00006b 16 00006c 16 00006d 16 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 count start register 0 one-shot start register 0 up-down register 0 timer a clock division select register timer a0 register timer a1 register timer a2 register timer a3 register timer a4 register timer b0 register timer b1 register timer b2 register timer a1 mode register timer a0 mode register timer a2 mode register timer a3 mode register timer a4 mode register timer b0 mode register timer b1 mode register timer b2 mode register processor mode register 0 processor mode register 1 watchdog timer register particular function select register 0 particular function select register 1 debug control register 0 int 3 interrupt control register a-d conversion interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register watchdog timer frequency select register debug control register 1 int 4 interrupt control register uart1 transmit interrupt control register timer a2 interrupt control register timer b1 interrupt control register int 2 interrupt control register address comparison register 0 address comparison register 1 particular function select register 2 reserved area (note) note: do not write to this address. a-d register 4 a-d register 5 a-d register 6 a-d register 7 count start register 1 one-shot start register 1 reserved area (note) reserved area (note)
m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 10 fig. 3 location of sfrs (2) serial i/o pin control register 0000c0 16 0000c1 16 0000c2 16 0000c3 16 0000c4 16 0000c5 16 0000c6 16 0000c7 16 0000c8 16 0000c9 16 0000ca 16 0000cb 16 0000cc 16 0000cd 16 0000ce 16 0000cf 16 0000d0 16 0000d1 16 0000d2 16 0000d3 16 0000d4 16 0000d5 16 0000d6 16 0000d7 16 0000d8 16 0000d9 16 0000da 16 0000db 16 0000dc 16 0000dd 16 0000de 16 0000df 16 0000e0 16 0000e1 16 0000e2 16 0000e3 16 0000e4 16 0000e5 16 0000e6 16 0000e7 16 0000e8 16 0000e9 16 0000ea 16 0000eb 16 0000ec 16 0000ed 16 0000ee 16 0000ef 16 0000f0 16 0000f1 16 0000f2 16 0000f3 16 0000f4 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fa 16 0000fb 16 0000fc 16 0000fd 16 0000fe 16 0000ff 16 up-down register 1 timer a5 register timer a6 register timer a7 register timer a8 register timer a9 register timer a0 1 register timer a1 1 register timer a2 1 register timer a5 mode register timer a7 mode register timer a8 mode register timer a9 mode register comparator function select register 0 comparator function select register 1 comparator result register 0 a-d register 8 a-d register 9 a-d register 10 a-d register 11 reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) uart2 transmit interrupt control register uart2 receive interrupt control register timer a7 interrupt control register timer a5 interrupt control register timer a6 interrupt control register timer a8 interrupt control register timer a9 interrupt control register int 7 interrupt control register int 5 interrupt control register int 6 interrupt control register 0000a0 16 0000a1 16 0000a2 16 0000a3 16 0000a4 16 0000a5 16 0000a6 16 0000a7 16 0000a8 16 0000a9 16 0000aa 16 0000ab 16 0000ac 16 0000ad 16 0000ae 16 0000af 16 0000b0 16 0000b1 16 0000b2 16 0000b3 16 0000b4 16 0000b5 16 0000b6 16 0000b7 16 0000b8 16 0000b9 16 0000ba 16 0000bb 16 0000bc 16 0000bd 16 0000be 16 0000bf 16 pulse output control register pulse output data register 0 pulse output data register 1 waveform output mode register three-phase output data register 0 three-phase output data register 1 uart2 transmit/receive mode register uart2 band rate register (brg2) uart2 transmit buffer register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 000080 16 000081 16 000082 16 000083 16 000084 16 000085 16 000086 16 000087 16 000088 16 000089 16 00008a 16 00008b 16 00008c 16 00008d 16 00008e 16 00008f 16 000090 16 000091 16 000092 16 000093 16 000094 16 000095 16 000096 16 000097 16 000098 16 000099 16 00009a 16 00009b 16 00009c 16 00009d 16 00009e 16 00009f 16 address (hexadecimel notation) address (hexadecimel notation) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) reserved area (note) note: do not write to this address. reserved area (note) d-a control register d-a register 0 d-a register 1 dead-time timer position-data-retain function control register port p2 pin function control register uart2 receive buffer register reserved area (note) reserved area (note) clock control register 0 reserved area (note) reserved area (note) reserved area (note) timer a6 mode register a-d control register 2 comparator result register 1 reserved area (note) external interrupt input read-out register reserved area (note)
11 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers central processing unit (cpu) the cpu has 13 registers and is shown in figure 4. each of these registers is described below. accumulator a (a) accumulator a is the main register of the microcomputer. it consists of 16 bits and the low-order 8 bits can be used separately. data length flag m determines whether the register is used as 16-bit reg- ister or as 8-bit register. it is used as a 16-bit register when flag m is ??and as an 8-bit register when flag m is ?? flag m is a part of the processor status register (ps) which is described later. data operations such as calculations, data transfer, input/output, etc., are executed mainly through accumulator a. accumulator b (b) accumulator b has the same functions as accumulator a, but the use of accumulator b requires more instruction bytes and execution cycles than accumulator a. accumulator e accumulator e is a 32-bit register and consists of accumulator a (low-order 16 bits) and accumulator b (high-order 16 bits). it is used for 32-bit data processing. index register x (x) index register x consists of 16 bits and the low-order 8 bits can be used separately. index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is ??and as an 8-bit register when flag x is ?? flag x is a part of the processor status register (ps) which is described later. in index addressing modes in which register x is used as the index register, the contents of this address are added to obtain the real ad- dress. index register x functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). index register y (y) index register y consists of 16 bits and the low-order 8 bits can be used separately. the index register length flag x determines whether the register is used as 16-bit register or as 8-bit register. it is used as a 16-bit register when flag x is ??and as an 8-bit register when flag x is ?? flag x is a part of the processor status register (ps) which is described later. in index addressing modes in which register y is used as the index register, the contents of this address are added to obtain the real ad- dress. index register y functions as a pointer register which indicates an address of data table in instructions mvp, mvn, rmpa (repeat multiply and accumulate). 15 7 0 15 7 0 15 7 0 15 7 0 15 0 15 0 15 0 15 7 0 00000 ipl 2 ipl 1 ipl 0 nvmxd i zc dpr0 to dpr3 pc s y h y l x h x l b h b l a h a l accumulator a accumulator b index register x index register y stack pointer s program counter pc direct page registers dpr0 to dpr3 processor status register ps carry flag zero flag interrupt disable flag decimal mode flag index register length flag data length flag overflow flag negative flag processor interrupt priority level ipl 70 70 pg program bank register pg data bank register dt dt 15 7 0 15 7 0 a h a l b h b l accumulator e 31 0 fig. 4 register structure
12 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers stack pointer (s) stack pointer (s) is a 16-bit register. it is used during a subroutine call or interrupts. it is also used during stack, stack pointer relative, or stack pointer relative indirect indexed y addressing mode. program counter (pc) program counter (pc) is a 16-bit counter that indicates the low-order 16 bits of the next program memory address to be executed. there is a bus interface unit between the program memory and the cpu, so that the program memory is accessed through bus interface unit. this is described later. program bank register (pg) program bank register is an 8-bit register that indicates the high-or- der 8 bits of the next program memory address to be executed. when a carry occurs by incrementing the contents of the program counter, the contents of the program bank register (pg) is increased by 1. also, when a carry or borrow occurs after adding or subtracting the offset value to or from the contents of the program counter (pc) using the branch instruction, the contents of the program bank regis- ter (pg) is increased or decreased by 1, so that programs can be written without worrying about bank boundaries. data bank register (dt) data bank register (dt) is an 8-bit register. with some addressing modes, the data bank register (dt) is used to specify a part of the memory address. the contents of data bank register (dt) is used as the high-order 8 bits of a 24-bit address. addressing modes that use the data bank register (dt) are direct indirect, direct indexed x indi- rect, direct indirect indexed y, absolute, absolute bit, absolute in- dexed x, absolute indexed y, absolute bit relative, and stack pointer relative indirect indexed y. direct page registers 0 through 3 (dpr0 through dpr3) the direct page register is a 16-bit register. an addressing mode of which name includes ?irect?generates an address of data to be ac- cessed, regarding the contents of this register as the base address. the 7900 series has been expanded direct page registers up to 4 (dpr0 to dpr3), in comparison to the 7700 series which has the single direct page register. accordingly, the 7900 seriess direct ad- dressing method which uses direct page registers differs from that of the 7700 series. however, the conventional direct addressing method, using only dpr0, is still be selectable, in order to make use of the 7700 series software property. for more details, refer to the section on the direct page. processor status register (ps) processor status register (ps) is an 11-bit register. it consists of flags to indicate the result of operation and cpu interrupt levels. branch operations can be performed by testing the flags c, z, v, and n. the details of each bit of the processor status register are described below. 1. carry flag (c) the carry flag contains the carry or borrow generated by the alu af- ter an arithmetic operation. this flag is also affected by shift and ro- tate instructions. this flag can be set and reset directly with the sec and clc instructions or with the sep and clp instructions. 2. zero flag (z) the zero flag is set if the result of an arithmetic operation or data transfer is zero and reset if it is not. this flag can be set and reset directly with the sep and clp instructions. 3. interrupt disable flag (i) when the interrupt disable flag is set to ?? all interrupts except watchdog timer and software interrupts are disabled. this flag is set to ??automatically when an interrupt is accepted. it can be set and reset directly with the sei and cli instructions or sep and clp in- structions. 4. decimal mode flag (d) the decimal mode flag determines whether addition and subtraction are performed as binary or decimal. binary arithmetic is performed when this flag is ?? if it is ?? decimal arithmetic is performed with each word treated as 2- or 4- digit decimal. arithmetic operation is performed using four digits when data length flag m is ??and with two digits when it is ?? decimal adjust is automatically performed. (decimal operation is possible only with the adc and sbc instruc- tions.) this flag can be set and reset with the sep and clp instruc- tions.
13 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 5. index register length flag (x) the index register length flag determines whether index register x and index register y are used as 16-bit registers or as 8-bit registers. the registers are used as 16-bit registers when flag x is ??and as 8- bit registers when it is ?? this flag can be set and reset with the sep and clp instructions. 6. data length flag (m) the data length flag determines whether the data length is 16-bit or 8-bit. the data length is 16 bits when flag m is ??and 8 bits when it is ?? this flag can be set and reset with the sem and clm instruc- tions or with the sep and clp instructions. 7. overflow flag (v) the overflow flag is valid when addition or subtraction is performed with a word treated as a signed binary number. if data length flag m is ?? the overflow flag is set when the result of addition or subtrac- tion is outside the range between ?2768 and +32767. if data length flag m is ?? the overflow flag is set when the result of addition or subtraction is outside the range between ?28 and +127. it is reset in all other cases. the overflow flag can also be set and reset directly with the sep, and clv or clp instructions. additionally, the overflow flag is set when a result of unsigned/signed division exceeds the length of the register where the result is to be stored; the flag is also set when the addition result is outside range of ?147483648 to +2147483647 in the rmpa operation. 8. negative flag (n) the negative flag is set when the result of arithmetic operation or data transfer is negative (if data length flag m is ?? datas bit 15 is ?? if data length flag m is ?? datas bit 7 is ??) it is reset in all other cases. it can also be set and reset with the sep and clp instruc- tions. 9. processor interrupt priority level (ipl) the processor interrupt priority level (ipl) consists of 3 bits and de- termines the priority of processor interrupts from level 0 to level 7. interrupt is enabled when the interrupt priority of the device request- ing interrupt (set using the interrupt control register) is higher than the processor interrupt priority. when an interrupt is enabled, the cur- rent processor interrupt priority level is saved in a stack and the pro- cessor interrupt priority level is replaced by the interrupt priority level of the device requesting the interrupt. refer to the section on inter- rupts for more details. note: fix bits 11 to 15 of the processor status register (ps) to ??
14 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers bank in order to effectively use the integrated hardware on the chip, this cpu core uses an address generating method with a 24-bit address split into high-order 8 bits and low-order 16 bits. in other words, the 64 kbytes specified by the low-order 16 bits are one unit (referred to as ?ank?, and the address space is divided into 256 banks (0 16 to ff 16 ) specified by the high-order 8 bits. in the program area on the address space, the bank is specified by the program bank register (pg), and the address in the bank is specified by the program counter (pc). as for each bank boundary, when an overflow has occurred in pc, the contents of pg are incremented by 1. when a borrow has oc- curred in pc, the contents of pg are decremented by 1. under the normal conditions, therefore, programming without concern for the bank boundaries is possible. furthermore, as for the data area on the address space, the bank is specified by the data bank register (dt), and the address in the bank is specified by the operation result by using the various addressing modes (note). note: some addressing modes directly specify a bank. direct page the internal memory and control registers for internal peripheral de- vices, etc. are assigned to bank 0 16 (addresses 0 16 to ffff 16 ). the direct page and direct addressing modes have been provided for the effective access to bank 0 16 . in the 7900 series, two types of direct addressing modes are available: the conventional direct addressing mode which uses only dpr0, as in the 7700 series, and the ex- panded direct addressing mode, which uses up to 4 direct page reg- isters as selected by the user. the addressing mode is selected according to the contents of bit 1 of the processor mode register 1. this bit 1 is cleared to ??at reset. (in other words, the conventional direct addressing mode is selected.) however, once this bit 1 has been set to ??by software, this bit cannot be cleared to ??again, except by reset. that is to say, when one of these two direct address- ing modes has been selected just after reset, the selected address- ing mode cannot be switched to another one while the program is running. conventional direct addressing mode the direct page area consists of 256-byte space. its bank address is ?0 16 ? and the base address of its low-order 16-bit address is speci- fied by the contents of the direct page register 0 (dpr0). in this con- ventional direct addressing modes, a value (1 byte) just after an instruction code is regarded as an offset value for the dpr0 con- tents, and the cpu accesses each address in the direct page area. expanded direct addressing mode the direct page area consists of four 64-byte spaces. their bank address is ?0 16 ? and the four base addresses of their low-order 16- bit addresses are respectively specified by the contents of four direct page registers. in this expanded direct addressing mode, a value (1 byte) just after an instruction code is regarded as follows: ?high-order 2 bits: regarded as a selection field for dpr0 to dpr3. ?low-order 6 bits: regarded as an offset value for the selected direct page register. then, the cpu accesses each address in each direct page area: refer to ?900 series software manual?for details concerning the various addressing modes which use the direct page area. instruction set the cpu core of the 7900 series has an expanded instruction set based on the existing 7700/7751 series?cpu core. in addition, its source code (mnemonic) has the complete upper compatibility with the 7700 series instruction set. for details concerning addressing modes and instruction set, refer to ?900 series software manual?
15 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers bus interface unit data transfer between the central processing unit (cpu) and inter- nal memory, internal peripheral devices is always performed via the bus interface unit (biu), which is located between the cpu and the internal buses. figure 5 shows the biu and the bus structure. the cpu and biu are connected by a dedicated bus, and any transfer between the cpu and biu is controlled by this dedicated bus. on the other hand, data transfer between the biu and internal pe- fig. 5 biu and bus structure internal code bus (cb 0 to cb 31 ) central processing unit (cpu) sfr : special function register ? the cpu bus and internal bus separate out independently. cpu bus internal buses internal data bus (db 0 to db 15 ) internal memory internal peripheral devices (sfr) internal address bus (ad 0 to ad 23 ) m37905 bus interface unit (biu) internal control signal ripheral devices uses the following internal common buses: 32-bit code bus, 16-bit data bus, 24-bit address bus, and control signals. the bus control method where the code bus and the data bus sepa- rate out (hereafter, this method is referred to as the separate code/ data bus method) is employed in order to improve data transfer ca- pabilities. as a result, the internal memory is connected to both the code bus and the data bus, and registers of all other internal periph- eral devices are connected only to the data bus.
16 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers name program address register instruction queue buffer data address register data buffer biu structure the biu consists of four registers shown in figure 6. table 1 lists the functions of each register. table 1. functions of each register fig. 6 register structure of biu functions indicates a storage address for an instruction to be next taken into an instruction queue buffer. temporarily stores an instruction which has been taken from a memory. consists of 10 bytes. indicates an address where data will be next read from or written to. temporarily stores data which has been read from internal memory or internal peripheral devices by the biu; or temporarily stores data which is to be written to internal memory or internal peripheral devices by the cpu. consists of 32 bits. pa q0 q9 da dq b23 b0 b7 b0 b23 b0 b31 b0 program address register instruction queue buffer data address register data buffer
17 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers x 0 0 ad 1 (a 1 ) even address 4-byte boundary 8-byte boundary biu functions (1) instruction prefetch the biu has ten instruction queue buffers; each buffer consists of 1 byte. when there is an opening in the bus and the instruction queue buffer, an instruction code is read from the program memory (in other words, the memory where a program is stored) and prefetched into an instruction queue buffer. the prefetched instruction code is trans- ferred from the biu to the cpu, in response to a request from the cpu, via a dedicated bus. when a branch occurs as a result of a branch instruction (jmp, bra, etc.), subroutine call, or interrupt, the contents of the instruction queue buffer are initialized and the biu reads a new instruction from the branch destination address. note that the operations of the biu instruction prefetch also differ de- pending on the store addresses for instructions. the store addresses for instructions to be prefetched are categorized as listed in table 2. (2) data read operation when executing an instruction for reading data from the internal memory or internal peripheral devices, at first, the cpu informs the bius data address register of the address where the data has been located. next, the biu reads the above data from the specified address, passes it to the data buffer, and then, transfers it to the cpu. (3) data write operation when executing an instruction for writing data into the internal memory or internal peripheral devices, at first, the cpu informs the bius data address register of the address where the data has been located. next, the biu passes the above data to the data buffer register, and then, writes it into the specified address. (4) bus cycle in order for the biu to execute the above operations (1) through (3), the 24-bit address bus, 32-bit code bus, 16-bit data bus and internal control signals must be appropriately controlled during data transfer between the biu and internal memory or internal peripheral devices. this operation is called ?us cycle? the bus cycle is affected by the lengh of data to be transferred (byte, word, or double-word) at data access. table 2. store addresses for instructions to be prefetched low-order 3 bits of store address for instruction ad 2 (a 2 ) x x 0 0 0 0 ad 0 (a 0 ) figures 7 and 8 show the bus cycle waveform examples for instruc- tion prefetch and data access. x: 0 or 1 fig. 7 bus cycle waveform example for instruction prefetch access to internal area when branched or at instruction prefetch biu internal address bus internal code bus cb 0 to cb 31 code address
18 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers access to internal area 8-bit data read 8-bit data written 16-bit data read 16-bit data written access starting from even address access starting from odd address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 0 to d 7 address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 0 to d 7 address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 address biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 0 to d 7 address 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 d 0 to d 7 address d 8 to d 15 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 8 to d 15 1 a 0 to a 23 d 0 to d 7 d 8 to d 15 address address + 1 d 8 to d 15 d 0 to d 7 d 8 to d 15 invalid invalid invalid invalid address address + 1 address 32-bit data read 32-bit data written biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 address address + 2 d 8 to d 15 d 0 to d 7 d 0 to d 7 d 8 to d 15 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 address address + 1 address + 3 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 0 to d 7 biu internal data bus db 0 to db 7 db 8 to db 15 d 8 to d 15 d 0 to d 7 d 8 to d 15 d 0 to d 7 biu internal address bus internal data bus db 0 to db 7 db 8 to db 15 d 8 to d 15 d 0 to d 7 d 0 to d 7 d 8 to d 15 invalid invalid address address + 2 address address + 1 address + 3 internal address bus fig. 8 bus cycle waveform example for data access (access to internal area)
19 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 9 bus cycle waveform at access to internal area 1 bus cycle = 3 (internal rom bus cycle select bit = 0) rom ram sfr internal address bus internal data bus, internal code bus biu address 1 bus cycle = 2 biu internal address bus internal data bus internal code bus address 1 bus cycle = 2 1 bus cycle = 2 (internal rom bus cycle select bit = 1) biu internal address bus internal data bus, internal code bus address data 1 bus cycle = 3 data data note: when reprogramming the internal flash memory in the cpu reprogramming mode, select the bus cycle = 3 . number of bus cycles figure 9 shows the bus cycle waveform at access to the internal area. bit 7 of the processor mode register 1 (address 5f 16 ), which is shown in figure 10, selects the number of bus cycles for the internal rom: 3 or 2 . (this bit 7 is the internal rom bus cycle select bit.) the internal ram, sfrs (internal peripheral devices?control regis- ters) are always accessed with 1 bus cycle = 2 . fig. 10 bit configuration of processor mode register 1 76543210 processor mode register 1 fix these bits to 0000000 2 . address 5f 16 internal rom bus cycle select bit 0 : 1 bus cycle = 3 1 : 1 bus cycle = 2 0000000
20 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers processor modes this microcomputer is dedicated to the single-chip mode. therefore, be sure to connect pin md0 to vss, and be sure to fix the processor mode bits (bits 1 and 0 of the processor mode register 0, address 5e 16 ), which is shown in figure 11, to ?0 2 ? fig. 11 bit configuration of processor mode register 0 76543210 processor mode register 0 processor mode bits 0 0 : single-chip mode 0 1 : do not select. 1 0 : do not select. 1 1 : do not select. interrupt priority detection time select bits 0 0 : 7 cycles of f sys 0 1 : 4 cycles of f sys 1 0 : 2 cycles of f sys 1 1 : do not select. software reset bit by a write of 1 to this bit, the microcomputer will be reset, and then, restarted. fix these bits to 00 2 . fix this bit to 0 . address 5e 16 00 0 00
21 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers interrupts table 3 shows the interrupt sources and the corresponding interrupt vector addresses. reset is also handled as an interrupt source in this section, too. dbc and brk instruction are interrupts used only for debugging. therefore, do not use these interrupts. interrupts other than reset, watchdog timer, zero divide, and address matching detection all have interrupt control registers. table 4 shows the addresses of the interrupt control registers and figure 13 shows the bit configuration of the interrupt control register. the interrupt request bit is automatically cleared by the hardware during reset or when processing an interrupt. also, interrupt request bits except for that of a watchdog timer interrupt can be cleared by software. an int i (i = 0 to 7) interrupt request is generated by an external in- put. int i is an external interrupt; whether to cause an interrupt at the in- put level (level sense) or at the edge (edge sense) can be selected with the level/edge select bit. furthermore, the polarity of the inter- rupt input can be selected with the polarity select bit. when using the following pins as external interrupt input pins, be sure to clear the direction registers of the corresponding multiplexed ports to ?? pins p5 1 /int 1 , p5 2 /int 2 , p5 3 /int 3 , p5 5 /int 5 , p5 6 /int 6 , and p5 7 /int 7 . when the external interrupt input read register (address 95 16 ), which is shown in figure 12, is read out, the status of pins int 0 through int 7 can directly be read. timer and uart interrupts are described in the respective section. the priority of interrupts when multiple interrupt requests are caused simultaneously is partially fixed by hardware, but, it can also be ad- justed by software as shown in figure 14. the hardware priority is fixed as the following: reset > watchdog timer > other interrupts interrupts uart2 transmit uart2 receive timer a9 timer a8 timer a7 timer a6 timer a5 int 7 external interrupt int 6 external interrupt int 5 external interrupt address matching detection interrupt int 4 external interrupt int 3 external interrupt a-d conversion uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 int 2 external interrupt int 1 external interrupt int 0 external interrupt watchdog timer dbc (do not select.) break instruction (do not select.) zero divide reset table 3. interrupt sources and interrupt vector addresses vector addresses 00ffb4 16 00ffb5 16 00ffb6 16 00ffb7 16 00ffb8 16 00ffb9 16 00ffba 16 00ffbb 16 00ffbc 16 00ffbd 16 00ffbe 16 00ffbf 16 00ffc0 16 00ffc1 16 00ffc2 16 00ffc3 16 00ffc4 16 00ffc5 16 00ffc6 16 00ffc7 16 00ffca 16 00ffcb 16 00ffd0 16 00ffd1 16 00ffd2 16 00ffd3 16 00ffd4 16 00ffd5 16 00ffd6 16 00ffd7 16 00ffd8 16 00ffd9 16 00ffda 16 00ffdb 16 00ffdc 16 00ffdd 16 00ffde 16 00ffdf 16 00ffe0 16 00ffe1 16 00ffe2 16 00ffe3 16 00ffe4 16 00ffe5 16 00ffe6 16 00ffe7 16 00ffe8 16 00ffe9 16 00ffea 16 00ffeb 16 00ffec 16 00ffed 16 00ffee 16 00ffef 16 00fff0 16 00fff1 16 00fff2 16 00fff3 16 00fff6 16 00fff7 16 00fff8 16 00fff9 16 00fffa 16 00fffb 16 00fffc 16 00fffd 16 00fffe 16 00ffff 16 fig. 12 bit configuration of external interrupt input read register 76543210 int 0 read bit int 1 read bit int 2 read bit int 3 read bit int 4 read bit int 5 read bit int 6 read bit int 7 read bit external interrupt input read register address 95 16
22 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 13 bit configuration of interrupt control register 76543210 interrupt priority level select bits (note 1) interrupt request bit 0 : no interrupt requested 1 : interrupt requested 76543210 interrupt priority level select bits (note 1) interrupt request bit (note 2) 0 : no interrupt requested 1 : interrupt requested polarity select bit 0 : interrupt request bit is set to 1 at h level when level sense is selected; this bit is set to 1 at falling edge when edge sense is selected. 1 : interrupt request bit is set to 1 at l level when level sense is selected; this bit is set to 1 at rising edge when edge sense is selected. level/edge select bit 0 : edge sense 1 : level sense interrupt control register bit configuration for a-d converter, uart0, uart1, uart2, timer a0 to timer a9, and timer b0 to timer b2. interrupt control register bit configuration for int 0 int 7 notes 1: use the movm (movmb) instruction or the sta (stab, stad) instruction for writing to this bit. 2: interrupt request bits of int 0 to int 7 are invalid when the level sense is selected.
23 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers interrupts caused by the address matching detection and when di- viding by zero are software interrupts and are not included in figure 14. other interrupts previously mentioned are a-d converter, uart, etc. interrupts. the priority of these interrupts can be changed by chang- ing the priority level in the corresponding interrupt control register by software. figure 15 shows a diagram of the interrupt priority detection circuit. when an interrupt is caused, each interrupt device compares its own priority with the priority from above and if its own priority is higher, then it sends the priority below and requests the interrupt. if the pri- orities are the same, the one above has priority. this comparison is repeated to select the interrupt with the highest priority among the interrupts that are being requested. finally the selected interrupt is compared with the processor interrupt priority level (ipl) contained in the processor status register (ps) and the request is accepted if it is higher than ipl and the interrupt disable flag i is 0 . the request is not accepted if flag i is 1 . the reset and watchdog timer interrupts are not affected by the interrupt disable flag i. when an interrupt is accepted, the contents of the processor status register (ps) is saved to the stack and the interrupt disable flag i is set to 1 . furthermore, the interrupt request bit of the accepted interrupt is cleared to 0 and the processor interrupt priority level (ipl) in the table 4. addresses of interrupt control registers interrupt control registers int 3 interrupt control register int 4 interrupt control register a-d interrupt control register uart0 transmit interrupt control register uart0 receive interrupt control register uart1 transmit interrupt control register uart1 receive interrupt control register timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register timer b2 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register uart2 transmit interrupt control register uart2 receive interrupt control register timer a5 interrupt control register timer a6 interrupt control register timer a7 receive control register timer a8 interrupt control register timer a9 interrupt control register int 5 interrupt control register int 6 interrupt control register int 7 interrupt control register addresses 00006e 16 00006f 16 000070 16 000071 16 000072 16 000073 16 000074 16 000075 16 000076 16 000077 16 000078 16 000079 16 00007a 16 00007b 16 00007c 16 00007d 16 00007e 16 00007f 16 0000f1 16 0000f2 16 0000f5 16 0000f6 16 0000f7 16 0000f8 16 0000f9 16 0000fd 16 0000fe 16 0000ff 16 fig. 14 interrupt priority fig. 15 interrupt priority detection watchdog timer reset priority is determined by hardware a-d converter, uart, etc. interrupts priority can be changed by software inside ? . ??? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int 2 int 1 int 0 reset a-d uart1 transmit uart1 receive uart0 transmit uart0 receive timer b2 timer b1 timer b0 timer a4 timer a3 timer a2 timer a1 timer a0 watchdog timer ipl interrupt request level 0 interrupt disable flag i int 3 int 7 int 6 int 5 int 4 timer a9 timer a8 timer a7 timer a6 timer a5 uart2 transmit uart2 receive
24 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers processor status register (ps) is replaced by the priority level of the accepted interrupt. therefore, multi-level priority interrupts are possible by resetting the interrupt disable flag i to 0 and enable further interrupts. for reset, watchdog timer, zero divide, and address match detection interrupts, which do not have an interrupt control register, the proces- sor interrupt level (ipl) is set as shown in table 5. the interrupt request bit and the interrupt priority level of each inter- rupt source are sampled and latched at each operation code fetch cycle while f sys is h . however, no sampling pulse is generated until the cycles whose number is selected by software has passed, even if the next operation code fetch cycle is generated. the detection of an interrupt which has the highest priority is performed during that time. as shown in figure 16, there are three different interrupt priority de- tection time from which one is selected by software. after the se- lected time has elapsed, the highest priority is determined and is processed after the currently executing instruction has been com- pleted. the time is selected with bits 4 and 5 of the processor mode register 0 (address 5e 16 ) shown in figure 11. table 6 shows the relationship between these bits and the number of cycles. after a reset, the pro- cessor mode register 0 is initialized to 00 16. therefore, the longest time is automatically set, however, the shortest time must be se- lected by software. table 5. value loaded in processor interrupt level (ipl) during an interrupt interrupt types reset watchdog timer zero divide address matching detection setting value 0 7 not change value of ipl. not change value of ipl. table 6. relationship between interrupt priority detection time select bit and number of cycles priority detection time select bit bit 5 0 0 1 bit 4 0 1 0 7 cycles of f sys 4 cycles of f sys 2 cycles of f sys number of cycles (note) fig. 16 interrupt priority detection time operation code fetch cycle f sys sampling pulse priority detection time select one between 00 to 10 with bits 4 and 5 of processor mode register 0 ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 1 1 0 b5 b4 (note) note: this pulse resides when 2 cycles of f sys is selected. note: for system clock f sys , refer to the section on the clock gener- ating circuit.
25 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 17 bit configuration of port p2 pin function control register 76543210 port p2 pin function control register pin tb0 in select bit 0: allocate pin tb0 in to p5 5 . 1: allocate pin tb0 in to p2 4 . pin tb2 in select bit 0: allocate pin tb2 in to p5 7 . 1: allocate pin tb2 in to p2 6 . address ae 16 pin tb1 in select bit 0: allocate pin tb1 in to p5 6 . 1: allocate pin tb1 in to p2 5 .
26 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers timer there are eight 16-bit timers. they are divided by type into timer a (10) and timer b (3). the timer i/o pins are multiplexed with i/o pins for ports p2, p4, p5 and p6. to use these pins as timer input pins, the port direction reg- ister bit corresponding to the pin must be cleared to 0 to specify input mode. timer a figure 18 shows a block diagram of timer a. timer a has four modes: timer mode, event counter mode, one-shot pulse mode, and pulse width modulation mode. the mode is se- lected with bits 0 and 1 of the timer ai mode register (i = 0 to 9). each of these modes is described below. figure 19 shows the bit configuration of the timer a clock division se- lect register. timers a0 to a9 use the count source which has been selected by bits 0 and 1 of this register. (1) timer mode [00] figure 20 shows the bit configuration of the timer ai mode register in the timer mode. bits 0, 1 and 5 of the timer ai mode register must be 0 in timer mode. the timer a s count source is selected by bits 6 and 7 of the timer ai mode register and the contents of the timer a clock division select register. (see table 7.) the counting of the selected clock starts when the count start bit is 1 and stops when it is 0 . figure 21 shows the bit configuration of the count start bit. the counter is decremented, an interrupt is caused and the interrupt re- quest bit in the timer ai interrupt control register is set when the con- tents becomes 0000 16 . at the same time, the contents of the reload register is transferred to the counter and count is continued. fig. 18 block diagram of timer a ?timer ?one-shot pulse ?pulse width count start registers 0, 1 (addresses 40 16 , 41 16 ) countdown data bus (odd) data bus (even) reload register(16) counter (16) (low-order 8 bits) (high-order 8 bits) ?ountdown?is always selected when not in the event counter mode. timer a0 47 16 46 16 timer a1 49 16 48 16 timer a2 4b 16 4a 16 timer a3 4d 16 4c 16 timer a4 4f 16 4e 16 countup/countdown switching toggle flip-flop up-down registers 0, 1 (addresses 44 16 , c4 16 ) polarity selection addresses external trigger event counter tai in (i = 0?) tai out (i = 0?) timer (gate function) count source select bits pulse output f 1 f 2 f 16 f 64 f 512 f 4096 timer a clock division select bit timer a5 c7 16 c6 16 timer a6 c9 16 c8 16 timer a7 cb 16 ca 16 timer a8 cd 16 cc 16 timer a9 cf 16 ce 16 addresses
27 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers when bit 2 of the timer ai mode register is 1 , the output is gener- ated from tai out pin. the output is toggled each time the contents of the counter reaches to 0000 16 . when the contents of the count start bit is 0 , l is output from tai out pin. when bit 2 is 0 , tai out can be used as a normal port pin. when bit 4 is 0 , tai in can be used as a normal port pin. when bit 4 is 1 , counting is performed only while the input signal from the tai in pin is h or l as shown in figure 22. therefore, this can be used to measure the pulse width of the tai in input signal. whether to count while the input signal is h or while it is l is de- termined by bit 3. if bit 3 is 1 , counting is performed while the tai in pin input signal is h and if bit 3 is 0 , counting is performed while it is l . note that, the duration of h or l on the tai in pin must be 2 or more cycles of the timer count source. when data is written to timer ai register with timer ai halted, the same data is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. when the value set in the timer ai register is n, the timer frequency division ratio is 1/(n+1). 0 0 : always 00 in timer mode 0 : no pulse output (tai out is normal port pin.) 1 : pulse output (tai out is pulse output pin.) 0 : no gate function (tai in is normal port pin.) 1 0 : count only while tai in input is l . 1 1 : count only while tai in input is h . 0 : always 0 in timer mode. clock source select bits see table 7. timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register 7 00 6543210 addresses 56 16 57 16 58 16 59 16 5a 16 0 timer a5 mode register timer a6 mode register timer a7 mode register timer a8 mode register timer a9 mode register addresses d6 16 d7 16 d8 16 d9 16 da 16 fig. 20 bit configuration of timer ai mode register in timer mode fig. 19 bit configuration of timer a clock division select register table 7. relationship between timer a clock division select bits, clock source select bits, and count source timer a clock division select bit (see table 7.) 76543210 timer a clock division select register address 45 16 clock source select bits (bits 7 and 6 at addresses 56 16 to 5a 16 ) (bits 7 and 6 at addresses d6 16 to da 16 ) 1 0 0 0 0 1 timer a clock division select bits (bits 1 and 0 at address 45 16 ) f 2 f 16 f 64 1 1 f 512 00 f 1 f 16 f 64 f 4096 01 f 1 f 64 f 512 f 4096 10 11 do not select. note: timers a0 to a9 use the same clock, which is selected by the timer a clock division select bits.
28 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 21 bit configuration of count start register fig. 22 count waveform when gate function is available 76543210 timer a0 count start bit timer a1 count start bit timer a2 count start bit timer a3 count start bit timer a4 count start bit timer b0 count start bit timer b1 count start bit timer b2 count start bit count start register 0 (stopped at 0 , started at 1 ) address 40 16 76543210 timer a5 count start bit timer a6 count start bit timer a7 count start bit timer a8 count start bit timer a9 count start bit count start register 1 (stopped at 0 , started at 1 ) address 41 16 selected clock source fi tai in bit 4 bit 3 10 timer mode register bit 4 bit 3 11 timer mode register
29 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers (2) event counter mode [01] figure 23 shows the bit configuration of the timer ai mode register in the event counter mode. in event counter mode, bit 0 of the timer ai mode register must be 1 and bits 1 and 5 must be 0 . the input signal from the tai in pin is counted when the count start bit shown in figure 21 is 1 and counting is stopped when it is 0 . count is performed at the fall of the input signal when bit 3 is 0 and at the rise of the signal when it is 1 . in event counter mode, whether to increment or decrement the count can be selected with the up-down bit or the input signal from the tai out pin. when bit 4 of the timer ai mode register is 0 , the up-down bit is used to determine whether to increment or decrement the count (decrement when the bit is 0 and increment when it is 1 ). figure 24 shows the bit configuration of the up-down register. when bit 4 of the timer ai mode register is 1 , the input signal from the tai out pin is used to determine whether to increment or decre- ment the count. however, note that bit 2 must be 0 if bit 4 is 1 . it is because if bit 2 is 1 , tai out pin becomes an output pin to output pulses. the count is decremented when the input signal from the tai out pin is l and incremented when it is h . determine the level of the input signal from the tai out pin before a valid edge is input to the tai in pin. an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set when the counter reaches 0000 16 (decrement count) or ffff 16 (increment count). at the same time, the contents of the reload register is transferred to the counter and the count is continued. when bit 2 is 1 , each time the counter reaches 0000 16 (decrement fig. 23 bit configuration of timer ai mode register in event counter mode 76543210 1 0 01 in event counter mode 0 : no pulse output 1 : pulse output 0 : count at the falling edge of input signal 1 : count at the rising edge of input signal 0 : increment or decrement according to up/down bit 1 : increment or decrement according to tai out pin input signal level 0 : always 0 in event counter mode count) or ffff 16 (increment count), the waveform s polarity is re- versed and is output from tai out pin. if bit 2 is 0 , tai out pin can be used as a normal port pin. however, if bit 4 is 1 and the tai out pin is used as an output pin, the output from the pin changes the count direction. therefore, bit 4 must be 0 unless the output from the tai out pin is to be used to se- lect the count direction. data write and data read are performed in the same way as for timer mode. that is, when data is written to timer ai halted, it is also writ- ten to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. the counter can be read at any time. in event counter mode, whether to increment or decrement the counter can also be determined by supplying two kinds of pulses of which phases differ by 90 to timer a2, a3, a4, a7, a8 or a9. there are two types of two-phase pulse processing operations. one uses timers a2, a3, a7, and a8 and the other uses timers a4 and a9. in both processing operations, two pulses described above are input to the ta jout (j = 2 to 4, 7 to 9) pin and taj in pin respectively. when timers a2, a3, a7, and a8 are used, as shown in figure 25, the count is incremented when a rising edge is input to the tak in (k=2, 3, 7, 8) pin after the level of tak out pin changes from l to h , and when the falling edge is input, the count is decremented. for timers a4 and a9, as shown in figure 26, when a phase-related pulse with a rising edge input to the tal in (l = 4, 9) pin is input after the level of tal out pin changes from l to h , the count is incremented at the respective rising edge and falling edge of the tal out pin and tal in pin.
30 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers when a phase-related pulse with a falling edge input to the tak out pin is input after the level of tal in pin changes from h to l , the count is decremented at the respective rising edge and falling edge of the tal in pin and tal out pin. when performing this two-phase pulse signal processing, bits 0 and 4 of timer aj mode register must be set to 1 and bits 1, 2, 3, and 5 must be 0 . bits 6 and 7 are ig- nored. (see figure 27.) note that bits 5, 6, and 7 of the up-down reg- ister 0 (address 44 16 ) are the two-phase pulse signal processing select bits for timers a2, a3, and a4, respectively. also, bits 5, 6, and 7 of the up-down register 1 (address c4 16 ) are the two-phase pulse signal processing select bits for timers a7, a8, and a9, respectively. each timer operates in normal event counter mode when the corre- sponding bit is 0 and performs two-phase pulse signal processing when it is 1 . count is started by setting the count start bit to 1 . data write and read are performed in the same way as for normal event counter mode. note that the direction register of the input port must be set to input mode because two kinds of pulse signals, described above, are input. also, there can be no pulse output in this mode. fig. 27 bit configuration of timer aj mode register when performing two-phase pulse signal processing in event counter mode fig. 25 two-phase pulse processing operation of timer a2, a3, a7, a8 fig. 26 two-phase pulse processing operation of timers a4 and a9 tak out decre- ment- count decre- ment- count decre- ment- count incre- ment- count incre- ment- count incre- ment- count tak in (k = 2, 3, 7, 8) fig. 24 bit configuration of up-down register timer a0 up-down bit timer a1 up-down bit timer a2 up-down bit timer a3 up-down bit timer a4 up-down bit timer a2 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a3 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a4 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode up-down register 0 address 44 16 76543210 timer a5 up-down bit timer a6 up-down bit timer a7 up-down bit timer a8 up-down bit timer a9 up-down bit timer a7 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a8 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode timer a9 two-phase pulse signal processing select bit 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing mode up-down register 1 address c4 16 76543210 tal out tal in (l = 4, 9) decrement-count at each edge increment-count at each edge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? decrement-count at each edge increment-count at each edge ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 76543210 1 0 0100 0 1 : always 01 in event counter mode 0 1 0 0 : always 0100 when processing two-phase pulse signal : not used in event counter mode timer a2 mode register timer a3 mode register timer a4 mode register timer a7 mode register timer a8 mode register timer a9 mode register addresses 58 16 59 16 5a 16 c8 16 c9 16 ca 16
31 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers (3) one-shot pulse mode [10] figure 28 shows the bit configuration of the timer ai mode register in the one-shot pulse mode. in one-shot pulse mode, bit 0 and bit 5 must be 0 and bit 1 and bit 2 must be 1 . the trigger is enabled when the count start bit is 1 . the trigger can be generated by software or it can be input from the tai in pin. soft- ware trigger is selected when bit 4 is 0 and the input signal from the tai in pin is used as the trigger when it is 1 . bit 3 is used to determine whether to trigger at the fall of the trigger signal or at the rise. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise of the trigger signal when it is 1 . software trigger is generated by setting 1 to a bit in the one-shot start register. each bit corresponds to each timer. figure 29 shows the bit configuration of the one-shot start register. as shown in figure 30, when a trigger signal is received, the counter counts the clock selected by bits 6 and 7 and the contents of the timer a clock division select register. (set table 7.) if the contents of the counter is not 0000 16 , the tai out pin goes h when a trigger signal is received. the count direction is decrement. when the counter reaches 0001 16 , the tai out pin goes l and count is stopped. the contents of the reload register is transferred to the counter. at the same time, an interrupt request signal is gener- ated and the interrupt request bit in the timer ai interrupt control reg- ister is set. this is repeated each time a trigger signal is received. 1 pulse frequency of the selected clock (counter s value at the time of trigger). fig. 28 bit configuration of timer ai mode register in one-shot pulse mode 76543210 0 1 1 0 1 0 : always 10 in one-shot pulse mode 1 : always 1 in one-shot pulse mode 0 0 in one-shot pulse mode clock source select bits (see table 7.) timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register address 56 16 57 16 58 16 59 16 5a 16 timer a5 mode register timer a6 mode register timer a7 mode register timer a8 mode register timer a9 mode register address d6 16 d7 16 d8 16 d9 16 da 16 the output pulse width is if the count start flag is 0 , tai out goes l . therefore, the value cor- responding to the desired pulse width must be written to timer ai be- fore setting the timer ai count start bit. as shown in figure 31, a trigger signal can be received before the operation for the previous trigger signal is completed. in this case, the contents of the reload register is transferred to the counter by the trigger and then that value is decremented. except when retriggering while operating, the contents of the reload register are not transferred to the counter by triggering. when retriggering, there must be at least one timer count source cycle before a new trigger can be issued. data write is performed in the same way as for timer mode. when data is written in timer ai halted, it is also written to the reload register and the counter. when data is written to timer ai which is busy, the data is written to the reload register, but not to the counter. the counter is reloaded with new data from the reload register at the next reload time. undefined data is read when timer ai is read.
32 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 30 pulse output example when external rising edge is selected fig. 31 example when trigger is re-issued during pulse output selected clock source fi tai in (rising edge) tai out example when the contents of the reload register is 0003 16 selected clock source fi tai in (rising edge) tai out example when the contents of the reload register is 0004 16 fig. 29 bit configuration of one-shot start register timer a0 one-shot start bit timer a1 one-shot start bit timer a2 one-shot start bit timer a3 one-shot start bit timer a4 one-shot start bit fix this bit to 0 . one-shot start register 0 address 42 16 76543210 0 timer a5 one-shot start bit timer a6 one-shot start bit timer a7 one-shot start bit timer a8 one-shot start bit timer a9 one-shot start bit fix this bit to 0 . one-shot start register 1 address 43 16 76543210 0
33 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers the width of the output pulse is changed by updating timer data. the update can be performed at any time. the output pulse width is changed at the rise of the pulse after data is written to the timer. the contents of the reload register are transferred to the counter just before the rise of the next pulse so that the pulse width is changed from the next output pulse. undefined data is read when timer ai is read. the 8-bit length pulse width modulator is described next. the 8-bit length pulse width modulator is selected when the timer ai mode register bit 5 is 1 . the reload register and the counter are both divided into 8-bit halves. the low-order 8 bits function as a prescaler and the high-order 8 bits function as the 8-bit length pulse width modulator. the prescaler counts the clock selected by bits 6, 7, and the contents of the timer a clock division select register. (see table 7.) a pulse is generated when the counter reaches 0000 16 as shown in figure 34. at the same time, the contents of the reload register is transferred to the counter and count is continued. therefore, if the low-order 8 bits of the reload register are n, the pe- riod of the generated pulse is (n + 1). the high-order 8 bits function as an 8-bit length pulse width modula- tor using this pulse as input. the operation is the same as for 16-bit length pulse width modulator except that the length is 8 bits. if the high-order 8 bits of the reload register are m, the duration h of pulse is and the output pulse period is (4) pulse width modulation mode [11] figure 32 shows the bit configuration of the timer ai mode register in the pulse width modulation mode. in pulse width modulation mode, bits 0, 1, and 2 must be set to 1 . bit 5 is used to determine whether to perform 16-bit length pulse width modulator or 8-bit length pulse width modulator. 16-bit length pulse width modulator is selected when bit 5 is 0 and 8-bit length pulse width modulator is selected when it is 1 . the 16-bit length pulse width modulator is described first. the pulse width modulator can be started with a software trigger or with an input signal from a tai in pin (external trigger). the software trigger mode is selected when bit 4 is 0 . pulse width modulator is started and a pulse is output from tai out when the count start bit is set to 1 . the external trigger mode is selected when bit 4 is 1 . pulse width modulation starts when a trigger signal is input from the tai in pin when the count start bit is 1 . whether to trigger at the fall or rise of the trigger signal is determined by bit 3. the trigger is at the fall of the trigger signal when bit 3 is 0 and at the rise when it is 1 . when data is written to timer ai with the pulse width modulator halted, it is written to the reload register and the counter. then when the count start bit is set to 1 and a software trigger or an external trigger is issued to start modulation, the waveform shown in figure 33 is output continuously. once modulation is started, triggers are not accepted. if the value in the reload register is m, the duration h of pulse is m and the output pulse period is (2 16 1). an interrupt request signal is generated and the interrupt request bit in the timer ai interrupt control register is set at each fall of the output pulse. 1 selected clock frequency 1 selected clock frequency fig. 32 bit configuration of timer ai mode register in pulse width modulation mode 76543210 1 1 : always 11 in pulse width modulation mode 1 : always 1 in pulse width modulation mode 0 1 selected clock frequency 1 selected clock frequency 1 selected clock frequency (n + 1) m. (n + 1) (2 8 1).
34 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 33 16-bit length pulse width modulator output pulse example fig. 34 8-bit length pulse width modulator output pulse example selected clock source fi tai in (rising edge) tai out 1/fi 1) 1/fi 1) 1/fi
35 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers timer b figure 35 shows a block diagram of timer b. timer b has three modes: timer mode, event counter mode, and pulse period measurement/pulse width measurement mode. the mode is selected with bits 0 and 1 of the timer bi mode register (i=0 to 2). each of these modes is described below. (1) timer mode [00] figure 36 shows the bit configuration of the timer bi mode register in the timer mode. bits 0 and 1 of the timer bi mode register must al- ways be ??in timer mode. bits 6 and 7 are used to select the clock source. the counting of the selected clock starts when the count start bit is ??and stops when ?? as shown in figure 21, the timer bis count start bits are allocated at the same address to which some of the timer ais count start bits are allocated. (in other words, they are allocated in the count start regis- ter 0.) the count is decremented, an interrupt occurs, and the inter- rupt request bit in the timer bi interrupt control register is set when the contents becomes 0000 16 . at the same time, the contents of the reload register is stored in the counter and count is continued. timer bi does not have a pulse output function or a gate function like timer a. when data is written to timer bi halted, it is written to the reload reg- ister and the counter. when data is written to timer bi which is busy, the data is written to the reload register, but not to the counter. the new data is reloaded from the reload register to the counter at the next reload time and counting continues. the contents of the counter can be read at any time. fig. 35 block diagram of timer b data bus (odd) data bus (even) reload register (16) counter (16) count start register 0 ?event counter mode notes 1: perform a write and read to/from timer bi register in the condition of 16-bit data length : data length flag (m) = ?? 2: only for timer b2, a count source in the event counter mode can be selected. (address 40 16 ) counter reset circuit ?timer mode ?pulse period measurement/pulse width measurement mode (low-order 8 bits) (high-order 8 bits) f 2 f 16 f 64 f 512 count source select bits f x 32 polarity selection and edge pulse generator tbi in timer b2 clock source select bit (note 2) timer b2 clock source select bit : bit 6 at address 63 16 addresses timer b0 51 16 50 16 timer b1 53 16 52 16 timer b2 55 16 54 16
36 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers (2) event counter mode [01] figure 37 shows the bit configuration of the timer bi mode register in the event counter mode. in event counter mode, bit 0 in the timer bi mode register must be ??and bit 1 must be ?? the input signal from the tbi in pin is counted when the count start bit is ??and counting is stopped when it is ?? count is performed at the fall of the input signal when bits 2 and 3 are ??and at the rise of the input signal when bit 3 is ??and bit 2 is ?? when bit 3 is ??and bit 2 is ?? count is performed at the rise and fall of the input signal. only for timer b2, when the timer b2 clock source select bit of the particular function select register 1 (bit 6 at address 63 16 ) = ??in the event counter mode, fx 32 can be selected. (when this bit is ?? an input signal from pin tb2 in becomes the count source as described above.) for the bit configuration of the particular function select reg- ister 1, refer to the section on the standby function. also, the pin position where pin tbi in is to be allocated can be se- lected by the pin tbi in select bit (bit 0, 1, or 2 at address ae 16 ; the port p2 pin function control register). (3) pulse period measurement/pulse width measurement mode [10] figure 38 shows the bit configuration of the timer bi mode register in the pulse period measurement/pulse width measurement mode. in the pulse period measurement/pulse width measurement mode, bit 0 must be ??and bit 1 must be ?? bits 6 and 7 are used to select the clock source. the selected clock is counted when the count start bit is ??and counting stops when it is ?? the pulse period measurement mode is selected when bit 3 is ?? in the pulse period measurement mode, the selected clock is counted during the interval starting at the fall of the input signal from the tbi in pin to the next fall or at the rise of the input signal to the next rise; the result is stored in the reload register. in this case, the reload register acts as a buffer register. when bit 2 is ?? the clock is counted from the fall of the input signal to the next fall. when bit 2 is ?? the clock is counted from the rise of the input signal to the next rise. in the case of counting from the fall of the input signal to the next fall, counting is performed as follows. as shown in figure 39, when the fall of the input signal from tbi in pin is detected, the contents of the counter is transferred to the reload register. next, the counter is cleared and count is started from the next clock. when the fall of the next input signal is detected, the contents of the counter is trans- ferred to the reload register once more, the counter is cleared, and the count is started. the period from the fall of the input signal to the next fall is measured in this way. after the contents of the counter is transferred to the reload register, an interrupt request signal is generated and the interrupt request bit in the timer bi interrupt control register is set. however, no interrupt request signal is generated when the contents of the counter is trans- ferred first to the reload register after the count start bit is set to ?? when bit 3 is ?? the pulse width measurement mode is selected. the pulse width measurement mode is the same as the pulse period measurement mode except that the clock is counted from the fall of the tbi in pin input signal to the next rise or from the rise of the input signal to the next fall as shown in figure 40. fig. 36 bit configuration of timer bi mode register in timer mode fig. 37 bit configuration of timer bi mode register in event counter mode fig. 38 bit configuration of timer bi mode register in pulse period measurement/pulse width measurement mode 0 0 : always 00 in timer mode 01 in event counter mode 0 0 : count at the falling edge of input signal 0 1 : count at the rising edge of input signal 1 0 : count at the both falling edge and rising edge of input signal 10 in pulse period measurement/pulse width measurement mode 0 0 : count from the falling edge of input signal to the next falling one 0 1 : count from the rising edge of input signal to the next rising one 1 0 : count from the falling edge of input signal to the next rising one and from the rising edge to the next falling one conut-type select bit 0 : counter-clear type 1 : free-run type timer bi overflow flag clock source select bits 0 0 : select f 2 0 1 : select f 16 1 0 : select f 64 1 1 : select f 512 76543210 0 1 timer b0 mode register timer b1 mode register timer b2 mode register address 5b 16 5c 16 5d 16
37 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers when timer bi is read, the contents of the reload register is read. note that in this mode, the interval between the fall of the tbi in pin input signal to the next rise or from the rise to the next fall must be at least two cycles of the timer count source. timer bi overflow flag which is bit 5 of timer bi mode register is set to ??when the timer bi counter reaches 0000 16 , which indicates that a pulse width or pulse period is longer than that which can be mea- sured by a 16-bit length. fig. 39 pulse period measurement mode operation (example of measuring the interval between the falling edge to next falling one ) fig. 40 pulse width measurement mode operation selected clock source fi tbi in reload register this flag is cleared by writing data to the corresponding timer bi mode register. this flag is set to ??t reset. in these modes, the count type can be selected by the count-type select bit (bit 4 of the timer bi mode register). when this bit = ?? the free-run type is selected; in this case, even when a valid edge is in- put to pin tbi in , the contents of the counter will not be cleared to ?000 16 ? and counting will continue. however, when a valid edge is input, an interrupt-requesting signal will be generated.
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 38 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers timer function for motor control three-phase motor drive waveform or pulse motor drive waveform can be output by using plural internal timers as. these modes are explained bellow. three-phase motor drive waveform output mode (three-phase waveform mode) three-phase waveform mode using timers a0, a1, a2 and a3 is se- lected by setting the waveform output select bits of the waveform output mode register (bits 2 through 0 at address a6 16 , figure 41) to ?00 2 ? there are two types of the three-phase waveform mode: three- phase mode 0 and three-phase mode 1. bit 4 of the waveform out- put mode register selects either mode. in the three-phase waveform mode, set the corresponding timer mode registers of timers a0, a1, and a2 to select the one-shot pulse mode with the rising edge of an external trigger valid; set the timer mode register of timer a3 to se- lect the timer mode. figure 43 shows the block diagram in the three-phase waveform mode. the three-phase waveform mode outputs six waveforms, positive waveforms (u, v, w phases) and negative waveforms (u, v, w phases), from the respective ports with ??level active. timer a2 controls u and u phases; timer a1 does v and v phases and timer a0 does w and w phases. timer a3 controls these one- shot pulses periods of timers a2, a1 and a0. in the waveform output, a short circuit prevention time can be set to prevent ??level of positive waveform outputs (u, v, w phases) from overlapping with ??level of their negative waveform outputs (u, v, w phases). the short circuit prevention time can be set with three 8- bit dead-time timers, sharing one reload register. the dead-time timer operates as a one-shot timer. its start trigger is selected from the following two types: both the rising and falling edges of timers a0 to a2s one-shot pulses or their falling edges. additionally, bit 6 of the waveform output mode register (address a6 16 ) controls this selec- tion. when that bit is ?? both the rising and falling edges are se- lected; when that bit is ?? the falling edges are selected. timer a0 mode register 56 16 timer a1 mode register 57 16 timer a2 mode register 58 16 76543210 0 1 11 0 address timer a3 mode register 59 16 76543210 0 0 address fix to ?0?in three-phase waveform mode fix to ?110?in three-phase waveform mode clock source select bits (see table 7.) 0 fix to ?00000?in three-phase waveform mode clock source select bits (see table 7.) 0 0 0 0 fig. 42 bit configuration of timer a0, a1, a2, mode register and timer a3 mode register in three-phase waveform mode waveform output mode register a6 16 76543210 0 0 1 address waveform output select bits 100 : fix to 100 in three-phase waveform mode (valid in three-phase mode 1) three-phase output polarity set buffer 0 : h output 1 : l output three-phase mode select bit 0 : three-phase mode 0 1 : three-phase mode 1 not used in three-phase waveform mode dead-time timer trigger select bit 0 : both edge of one-shot pulse with timers a2 to a0 1 : only the falling edge of one-shot pulse with timers a2 to a0 waveform output control bit 0 : waveform output disabled 1 : waveform output enabled fig. 41 bit configuration of waveform output mode register in three- phase waveform mode
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 39 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers fig. 43 block diagram in three-phase waveform mode dq t d q output polarity set toggle flip-flop 2 0 1 d q t r timer a3 (16) (timer mode) timer a2 reload timer a2 1 timer a2 counter (16) u-phase output polarity set buffer (bit 5 at address a9 16 ) t interval control d q r d q r timer a1 reload timer a1 1 timer a1 counter (16) v-phase output polarity set buffer (bit 4 at address a9 16 ) t timer a0 reload timer a0 1 timer a0 counter (16) w-phase output polarity set buffer (bit 3 at address a8 16 ) t three-phase output polarity set buffer (bit 3 at address a6 16 ) interrupt validity output select bit (bit 5 at address a9 16 ) three-phase mode select bit (bit 4 at address a6 16 ) d q output polarity set toggle flip-flop 0 0 1 d q output polarity set toggle flip-flop 1 0 1 reset interrupt request interval set bit (bit 4 at address a9 16 ) 1 0 reset q d r reset timer a3 interrupt request signal (one-shot pulse mode) (one-shot pulse mode) (one-shot pulse mode) reload register dead-time timer (8) t dead-time timer (8) t f 2 f 4 f 8 clock-source-of-dead-time-timer select bits (bits 7, 6 at address a8 16 ) d q t dead-time timer (8) t d q r reset p6out cut u v w u v w waveform output control bit (bit 7 at address a6 16 ) u-phase output fix bit (bit 2 at address a8 16 ) dq trigger generating circuit s r q t q v-phase output fix bit (bit 1 at address a8 16 ) dq dq t trigger generating circuit s r q t q w-phase output fix bit (bit 0 at address a8 16 ) dq dq t trigger generating circuit s r q t q u-phase output control circuit v-phase output control circuit w-phase output control circuit d q t d q t d q t d q t d q t u-phase output fix polarity set bit (bit 2 at address a9 16 ) w-phase output fix polarity set bit (bit 0 at address a9 16 ) v-phase output fix polarity set bit (bit 1 at address a9 16 ) 1/2 1/2 idu t q d t q d t q d b2 idv idw b1 b0 data bus (even-numbered) bits 2 through 0 of position- data-retain function control register (address aa 16 ) circuit
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 40 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers when writing data to the dead-time timer (address a7 16 ), the data is written to the reload register shared by three dead-time timers. when the dead-time timers catch the start trigger from the respec- tive timers, the reload register contents are transferred to its counter and the dead-time timer decrements with the clock source selected by bits 6 and 7 of three-phase output data register 0 (address a8 16 ). additionally, this timer can accept another trigger before completion of the preceding trigger operation. in this case, after transferring the reload register contents to the dead-time timer at acceptance of the trigger, the value is decremented. the dead-time timer operates as a one-shot pulse timer. accordingly, this timer starts pulse output when the trigger is caught, and finishes pulse output and stops operation when its contents become ?0 16 ? and waits next trigger. three-phase output data register 0 a8 16 76543210 address w-phase output fix bit 0 : released from output fixation 1 : output fixed v-phase output fix bit 0 : released from output fixation 1 : output fixed u-phase output fix bit 0 : released from output fixation 1 : output fixed when three-phase mode 0 is selected: w-phase output polarity set buffer 0 : h output 1 : l output when three-phase mode 1 is selected: it may be either 0 or 1 . in three-phase waveform mode, these bits are invalid. any of them may be either 0 or 1 . clock-source-of-dead-time-timer select bits 0 0 : f 2 0 1 : f 4 1 0 : f 8 1 1 : do not select. w-phase fixed output s polarity set bit 0 : h output fixed 1 : l output fixed v-phase fixed output s polarity set bit 0 : h output fixed 1 : l output fixed u-phase fixed output s polarity set bit 0 : h output fixed 1 : l output fixed in three-phase waveform mode, this bit is invalid. it may be either 0 or 1 . when three-phase mode 0 is selected: v-phase output polarity set buffer 0 : h output 1 : l output when three-phase mode 1 is selected: interrupt request interval set bit 0 : every second time 1 : every fourth time when three-phase mode 0 is selected: u-phase output polarity set buffer 0 : h output 1 : l output when three-phase mode 1 is selected: interrupt validity output select bit 0 : an interrupt request occurs at each even-numbered underflow of timer a3. 1 : an interrupt request occurs at each odd-numbered underflow of timer a3. in three-phase waveform mode, these bits are invalid. any of them may be either 0 or 1 . three-phase output data register 1 a9 16 76543210 address fig. 44 bit configuration of three-phase output data registers 1 and 0 in three-phase waveform mode in the three-phase waveform mode, setting bit 7 of the waveform output mode register (address a6 16 ) to ??makes positive wave- forms (u, v, w phases) and their negative waveforms (u, v, w phases) output from the respective ports. when this bit is ?? their ports are floating. this bit is cleared to ??by inputting a falling edge to pin p6out cut , by reset, or by executing instructions. additionally, setting bits 2 through 0 of the three-phase output data register 0 (address a8 16 ) to ??makes the corresponding waveform outputs fixed. whether the outputs are fixed to ??or ??is selected by bits 2 through 0 of the three-phase output data register 1 (address a9 16 ). clearing these bits to ??makes the corresponding waveform outputs fixed to ?? setting these bits to ??makes the outputs fixed to ??
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 41 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers three-phase mode 0 in selecting three-phase waveform mode, three-phase mode 0 is se- lected by setting bit 4 of the waveform output mode register (address a6 16 ) to ?? the output polarity of three-phase waveform depends on the output polarity set toggle flip-flop. the positive waveform of the three-phase waveform is ??output when the toggle flip-flop is ?? it is ??output when the toggle flip-flop is ?? (three-phase waveform is output as a negative waveform.) each output polarity set toggle flip-flop has the output polarity set buffer shown in figure 44. when the timer a3s counter contents be- come 0000 16 , the contents of output polarity set buffer are set into the output polarity set toggle flip-flop. after that, the polarity of the contents of output polarity set toggle flip-flop are reversed each time completion of one-shot pulse of timer (timers a2 to a0) correspond- ing to each phase. figure 45 shows an example of u-phase waveform and the output operation is explained. three-phase mode 0 becomes valid when writing ??to the u-phase output polarity set buffer (bit 5 at address a9 16 ) and actuating the timer a3. when the counter of timer a3 be- comes 0000 16 , the timer a3 interrupt request signal occurs and the timer a2 simultaneously starts one-shot pulse output. at this time, the contents of u-phase output polarity set buffer, ??in this case, are set into the output polarity set toggle flip-flop 2. when the one-shot pulse output of timer a2 is completed, the con- tents of output polarity set toggle flip-flop 2 is reversed from ??to ?? simultaneously, the one-shot pulse of the 8-bit dead-time timer is output for ensuring time not to overlap ??levels of u phase wave- form and its negative u phase waveform. the u-phase waveform output keeps ??level from the start until the one-shot pulse output of the dead-time timer is completed, even if the contents of output polarity set toggle flip-flop 2 are reversed from ??to ??owing to the timer a2s one-shot pulse output. when the one-shot pulse output of the dead-time timer is completed, ??of output polarity set toggle flip-flop 2 which has been reversed be- comes valid and the u phase waveform changes to ??level. signal output each time timer a3 becomes 0000 16 one-shot pulse output with timer a2 contents of output polarity set toggle flip-flop 2 reversed pulse output signal with dead-time timer u-phase waveform output u-phase waveform output then, write ??to the u-phase output polarity set buffer (bit 5 at ad- dress a9 16 ) before the counter of timer a3 becomes 0000 16 . after that, when the counter of timer a3 becomes 0000 16 , the timer a2 starts one-shot pulse output. simultaneously, the contents of u- phase output polarity set buffer, ??in this case, are set into the out- put polarity set toggle flip-flop 2 and the u phase waveform remains ??level. when the one-shot pulse output of timer a2 is completed, the con- tents of output polarity set toggle flip-flop 2 is reversed from ??to ?? simultaneously, the one-shot pulse output of the dead-time timer starts. when the contents of output polarity set toggle flip-flop 2 are re- versed from ??to ?? the u-phase waveform changes its output level from ??to ??without waiting for completion of the one-shot pulse output of the dead-time timer. u-phase waveform is generated by repeating the operation above. the way to generate u-phase waveform, which is the negative phase of u-phase, is the same as that for u-phase waveform except that the contents of output polarity set toggle flip-flop 2 are treated as the reversed signal from the case of u-phase waveform. in this way, u-phase waveform and u-phase waveform, having the negative phase of u-phase, are output from the pins so that their ? levels do not overlap each other. the width of ??level can be also modified by changing the value of timer a2 or a3. v-, w-phase waveform and v-, w-phase waveform, having their negative phase, are similarly output according to the corresponding timer operation. the explanation above is an example of three-phase waveform gen- erating due to an triangular wave modulation. three-phase wave- form due to a saw-tooth-wave modulation can also be generated by fixing each beginning level of phases. fig. 45 u-phase waveform output example in three-phase mode 0 (triangular wave modulation)
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 42 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers three-phase mode 1 in selecting three-phase waveform mode, three-phase mode 1 is selected by setting bit 4 of the waveform output mode register (ad- dress a6 16 ) to ?? in this mode, each of timers a0 to a2 can have two timer registers and the contents of those registers are alternately reloaded into the counter each time the counter of timer a3 becomes 0000 16 . the interrupt request normally occurs when the counter of timer a3 becomes 0000 16 . however, this occurrence interval can be switched between ?very second time?and ?very fourth time.?bit 4 of the pulse output data register 1 (address a9 16 ) selects that. additionally, an even-numbered or odd-numbered timer a3s under- flow can be used as the occurrence factor of timer a3 interrupt re- quest. bit 5 of the three-phase output data register 1 (address a9 16 ) selects that. when the timer a3s counter contents become 0000 16 , the contents of three-phase output polarity set buffer are set into the output polar- ity set toggle flip-flop on which the output polarity of three-phase waveform depends. the contents of three-phase output polarity set buffer are reversed after that operation. the polarity of the contents of output polarity set toggle flip-flop is re- versed each time completion of one-shot pulse of timer (timers a2 to a0) corresponding to each phase. figure 46 shows an example of u-phase waveform and the output operation is explained. write ??to the three-phase-output-polarity set buffer (bit 3 at ad- dress a6 16 ). clear the interrupt request interval set bit (bit 4 at ad- dress a9 16 ) to ??so that the timer a3 interrupt request occurs at every second time. additionally, clear the interrupt validity output se- lect bit (bit 5 at address a9 16 ) so that the timer a3 interrupt request occurs at an each even-numbered underflow of timer a3. after the procedure above, three-phase mode 1 starts operation when actuating timer a3. when the counter of timer a3 becomes 0000 16 , the timer a3 interrupt request occurs and timer a2 simultaneously starts one-shot pulse output. at this time, the contents of three-phase output polarity set buffer, ??in this case, are set into the output polarity set toggle flip- flop 2. the contents of three-phase output polarity set buffer are re- versed from ??to ??after that operation. when the timer a2 counter counts the value written into the timer a2 and the one-shot pulse output of timer a2 is completed, the contents of output polarity set toggle flip-flop 2 are reversed from ??to ?? si- multaneously, the one-shot pulse of the 8-bit dead-time timer is out- put for ensuring time, so that ??levels of u- and u-phase waveforms do not overlap. the u-phase waveform output keeps ??level from the start until the one-shot pulse output of the dead-time timer is completed, even if the contents of output polarity set toggle flip-flop 2 are reversed from ??to ??owing to the timer a2s one-shot pulse output. when the one-shot pulse output of the dead-time timer is completed, ??of output polarity set toggle flip-flop 2 which has been reversed becomes valid and the u-phase waveform changes to ??level. then, when the counter of timer a3 becomes 0000 16 , the timer a2 counter counts the value written into timer a2 and timer a2 starts one-shot pulse output. simultaneously, the contents of three-phase output polarity set buffer are set into the output polarity set toggle flip-flop 2. however, the u-phase waveform remains ??level, be- cause the value is the same (??. the contents of three-phase output polarity set buffer are reversed from ??to ??after that operation. when the one-shot pulse output of timer a2 is completed, the con- tents of output polarity set toggle flip-flop 2 is reversed from ??to ?? simultaneously, the one-shot pulse output of the dead-time timer starts. when the contents of output polarity set toggle flip-flop 2 is reversed from ??to ?? the u-phase waveform changes its output level from ??to ??without waiting for completion of the one-shot pulse output of the dead-time timer. u-phase waveform is generated by repeating the operation above. the way to generate u-phase waveform, which is the negative phase of u-phase, is the same as that for u-phase waveform except that the contents of output polarity set toggle flip-flop 2 is treated as the reversed signal from the case of u-phase waveform. in this way, u-phase waveform and u-phase waveform, having the negative phase of u-phase, are output from the pins so that their ? levels do not overlap each other. the width of ??level can be also modified by changing the value of timers a2, a2 1 , or a3. v-, w-phase waveform and v-, w-phase waveform, having their negative phase, are similarly output according to the corresponding timer operation.
preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 43 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers timer a3 interrupt request signal signal output each time timer a3 becomes 0000 16 one-shot pulse output with timer a2 timer a2 timer a2 1 contents of output polarity set toggle flip-flop 2 reversed pulse output signal with dead-time timer u-phase waveform output u-phase waveform output n1 n1 n3 n5 n7 n2 n4 n6 n8 n2 n3 n4 n5 n6 fig. 46 u-phase waveform output example in three-phase mode 1 (triangular wave modulation) position-data-retain function the three-phase waveform mode has the function to retain the input data of the corresponding pin (idu, idv, idw) at an edge of a posi- tive waveform (u, v, or w phase). whether to retain the data at a fall- ing edge or rising one is selected by bit 3 of the position-data-retain function control register (address aa 16 ). retain data can be read out by bits 2 through 0 of the position-data- retain function control register (address aa 16 ). fig. 47 bit configuration of position-data-retain function control register address position-data-retain function control register 76543210 w-phase position data retain bit (pin idw) v-phase position data retain bit (pin idv) u-phase position data retain bit (pin idu) retain-trigger polarity select bit 0 : falling edge of each phase? positive waveform 1 : rising edge of each phase? positive waveform aa 16
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 44 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers pulse output port mode 0 figure 48 shows the block diagram in the pulse output port mode 0. this mode has an 8-bit pulse output port. the waveform output se- lect bits (bits 0 to 2) of waveform output mode register (address a6 16 ) select use of pulse output port. the 8-bit pulse output port can also be divided into ? bits and 4 bits?or ? bits and 2 bits? with the pulse output mode select bit (bit 3) of waveform output mode regis- ter (address a6 16 ); each of them can be individually controlled. set timers a3 and a0 to the timer mode because they are used in the pulse output port mode 0. figure 50 shows the bit configuration of timer a3 and a0 mode registers in the pulse output port mode 0. timers a3 and a0 start count when setting the corresponding timer count start bit to ?? and they stop it when clearing that bit to ?? fig. 48 block diagram in pulse output port mode 0 each bit using timer a0 as a trigger can also be controlled by an in- put trigger from pin rtp trg0 . this control is selected by the pulse output trigger select bits of the three-phase output data register 0 (bits 7 and 6 at address a8 16 ). also, this externally-input trigger can be selected from the following three types: falling edges, rising edges, and falling and rising edges. the reversed content of the pulse output data bit can be output to each pulse output port by the pulse output polarity select bit of the three-phase output data register 1 (bit 3 at address a9 16 ). when the pulse output polarity select bit = ?? the content of the pulse output data bit is output as it is; when the pulse output polarity select bit = ?? the reversed content is output. b0 b1 b2 b0 b1 b2 b3 b4 b5 rtp1 0 rtp1 1 rtp0 3 d q d q d q d q d q t d q rtp0 1 rtp0 2 d q r t d q d q d q r rtp0 0 t d q b6 b7 d q d q t rtp1 2 rtp1 3 p6out cut pulse output polarity select bit (bit 3 at address a9 16 ) waveform output control bit 0 (bit 6 at address a6 16 ) reset pulse width modulation circuit pulse output trigger select bits (bits 7, 6 at address a8 16 ) pulse width modulation output of timer a1 pulse width modulation timer select bits (bits 5, 4 at address a6 16 ) pulse width modulation output of timer a2 pulse width modulation output of timer a4 timer a3 pulse width modulation enable bits 0 through 2 (bits 0 through 2 at address a9 16 ) timer a0 rtp trg1 bits 0 through 3 of three- phase output data register 0 (address a8 16 ) bits 4, 5 of three-phase output data register 0 (address a8 or 16 ) bits 4, 5 of three-phase output data register 1 (address a9 16 ) bits 6, 7 of three-phase output data register 1 (address a9 16 ) data bus (even-numbered) pulse output mode select bit (bit 3 at address a6 16 ) data bus (odd-numbered) waveform output control bit 1 (bit 7 at address a6 16 ) reset
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 45 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers fig. 49 bit configuration of waveform output mode register in pulse output port mode 0 timer a0 mode register 56 16 timer a3 mode register 59 16 fix these bits to 000000 in pulse output port mode. clock source select bits (see table 7.) 76543210 0 0 0 0 0 0 address fig. 50 bit configuration of timer a3 and a0 mode registers in pulse output port mode 0 waveform output select bits 000 : parallel ports 001 : when pulse mode 0 is selected, rtp0 is selected. when pulse mode 1 is selected, rtp0, rtp1 1 , rtp1 0 are selected. 010 : when pulse mode 0 is selected, rtp1 is selected. when pulse mode 1 is selected, rtp1 3 and rtp1 2 are selected. 011 : when pulse mode 0 is selected, rtp0 and rtp1 are selected. when pulse mode 1 is selected, rtp0, rtp1 1 , rtp1 0 and rtp1 3 , rtp1 2 are selected. pulse output mode select bit 0 : pulse mode 0 1 : pulse mode 1 pulse width modulation timer select bits 0 0 : when pulse mode 0 is selected (valid only for rtp0), pulse width modulation by timer a1 when pulse mode 1 is selected (valid only for rtp0, rtp1 1 , rtp1 0 ), pulse width modulation by timer a1 0 1 : when pulse mode 0 is selected, do not set. when pulse mode 1 is selected (valid only for rtp0, rtp1 1 , rtp1 0 ), pulse width modulation by timer a1 ; rtp0 2 , rtp0 1 , rtp0 0 pulse width modulation by timer a2 ; rtp0 3 , rtp1 1 , rtp1 0 1 0 : when pulse mode 0 is selected, do not set. when pulse mode 1 is selected (valid only for rtp0, rtp1 1 , rtp1 0 ), pulse width modulation by timer a1 ; rtp0 1 , rtp0 0 pulse width modulation by timer a2 ; rtp0 3 , rtp0 2 pulse width modulation by timer a4 ; rtp1 1 , rtp1 0 1 1 : do not select. waveform output control bit 0 when pulse mode 0 is selected, 0 : rtp1 waveform outputs is disabled. 1 : rtp1 waveform outputs is enabled. when pulse mode 1 is selected, 0 : rtp1 3 , rtp1 2 waveform outputs are disabled. 1 : rtp1 3 , rtp1 2 waveform outputs are enabled. waveform output control bit 1 when pulse mode 0 is selected, 0 : rtp0 waveform output is disabled. 1 : rtp0 waveform output is enabled. when pulse mode 1 is selected, 0 : rtp0, rtp1 1 , rtp1 0 waveform outputs are disabled. 1 : rtp0, rtp1 1 , rtp1 0 waveform outputs are enabled. 76543210 address waveform output mode register a6 16
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 46 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers rtp0 0 pulse output data bit rtp0 1 pulse output data bit rtp0 2 pulse output data bit rtp0 3 pulse output data bit rtp1 0 pulse output data bit; valid when pulse mode 1 is selected. rtp1 1 pulse output data bit; valid when pulse mode 1 is selected. pulse output trigger select bits 0 0 : underflow of timer a0 0 1 : falling edge of input signal to pin rtp trg0 1 0 : rising edge of input signal to pin rtp trg0 1 1 : falling and rising edges of input signal to pin rtp trg0 76543210 address three-phase output data register 1 a9 16 76543210 address three-phase output data register 0 a8 16 pulse width modulation enable bit 0 0 : no pulse width modulation by timer a1 1 : pulse width modulation by timer a1 pulse width modulation enable bit 1 0 : no pulse width modulation by timer a2 1 : pulse width modulation by timer a2 pulse width modulation enable bit 2 0 : no pulse width modulation by timer a4 1 : pulse width modulation by timer a4 pulse output polarity select bit 0 : positive 1 : negative rtp1 0 pulse output data bit; valid when pulse mode 0 is selected. rtp1 1 pulse output data bit; valid when pulse mode 0 is selected. rtp1 2 pulse output data bit rtp1 3 pulse output data bit fig. 51 bit configuration of three-phase output data registers 1 and 0 in pulse output port mode 0 pulse mode 0 this mode divides a pulse output port into 4 bits and 4 bits and indi- vidually controls them. when setting the pulse output mode select bit to 0 , and setting bits 2 and 1 to 0 and bit 0 to 1 of the waveform output select bits, four of rtp0 3 , rtp0 2 , rtp0 1 , and rtp0 0 become the pulse output ports (rtp0 selected). when setting the pulse output mode select bit to 0 , and setting bits 2 and 0 to 0 and bit 1 to 1 of the waveform output select bits, four of rtp1 3, rtp1 2, rtp1 1 , rtp1 0 become the pulse output ports (rtp1 selected). when setting the pulse output mode select bit to 0 , and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits, the following two groups become the pulse output ports: four of rtp1 3 , rtp1 2 , rtp1 1 , rtp1 0 four of rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 . each time the contents of timer a3 counter become 0000 16 , the con- tents of three-phase output data register 1 (address a9 16 ) s high or- der 4 bits, (bits 7 to 4), which corresponding to rtp1 3 , rtp1 2, rtp1 1 , rtp1 0 , are output from ports. each time the contents of timer a0 counter become 0000 16 , the con- tents of three-phase output data register 0 (address a8 16 ) s low or- der 4 bits (bits 3 to 0), which corresponding to rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 , are output from ports. when writing 0 to the specified one of the pulse output data bits, l level is output from the pulse output port when the contents of the corresponding timer counter become 0000 16 ; when writing 1 to it, h level is output from the pulse output port. in the case that an input trigger of pin rtp trg0 is selected, the data written to the pulse output data bit is output from the corresponding pulse output port by this selected trigger. additionally, pulse width modulation can be applied for rtp0 3 , rtp0 2 , rtp0 1 , and rtp0 0 . because timer a1 is used for pulse width modulation, actuate timer a1 in the pulse width modulation mode. when any of pulse output data bits is 1 , the pulse to which pulse width modulation has been applied is output from the pulse output port when the contents of timer a0 counter become 0000 16 . the pulse width modulation using timer a1 can be applied by setting the pulse width modulation enable bit 0 of the three-phase output data register 1 (bit 0 at address a9 16 ) to 1 and the pulse width modulation timer select bits of the waveform output mode register (bits 5 and 4 at address a6 16 ) to 00 . figure 52 shows example waveforms in pulse mode 0. in ports selecting pulse mode 0, output of rtp1 3 , rtp1 2 , of rtp1 1 and rtp1 0 is controlled by the waveform output control bit 0 (bit 6) of waveform output mode register; output of rtp0 3 , rtp0 2 , rtp0 1 and rtp0 0 is done by the waveform output control bit 1 (bit 7). when setting the waveform output control bit to 1 , waveform is out- put from the corresponding port. when clearing that bit to 0 , wave- form output from the corresponding port stops, and the port becomes floating. the waveform output control bits are cleared to 0 by reset or by executing instructions. also, the waveform output control bit 1 can be cleared to 0 by in- putting a falling edge to pin p6out cut .
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 47 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers pulse mode 1 this mode divides a pules output port into 6 bits and 2bits and indi- vidually control them. when setting the pulse output mode select bit to 1 , and setting bits 2 and 1 to 0 and bit 0 to 1 of the waveform output select bits, the following become the pulse output ports: six of rtp1 1 , rtp1 0 , rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 when setting the pulse output mode select bit to 1 , and setting bits 2 and 0 to 0 and bit 1 to 1 of the waveform output select bits, two of rtp1 3, rtp1 2 become the pulse output ports. when setting the pulse output mode select bit to 1 , and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits, the following two groups become the pulse output ports: two of rtp1 3 , rtp1 2 six of rtp1 1 , rtp1 0 , rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0. each time the contents of timer a3 counter become 0000 16, the con- tents of three-phase output data register 1 (address a9 16 ) s bits 7 and 6, which corresponding to rtp1 3 and rtp1 2 , are output from ports. each time the contents of timer a0 counter become 0000 16, the con- tents of three-phase output data register 0 (address a8 16 )s low or- der 6 bits (bits 5 to 0), which corresponding to rtp1 1 , rtp1 0 , rtp0 3, rtp0 2, rtp0 1, rtp0 0, are output from ports. whether to control these pulse output ports by an underflow of timer a0 or an input edge to pin rtp trg0 is selected by the pulse output trigger select bits of the three-phase output data register 0 (bits 7 and 6 at address a8 16 ). additionally, pulse width modulation can be applied to rtp1 1, rtp1 0, rtp0 3, rtp0 2, rtp0 1, and rtp0 0 . the pulse width modula- tion timer select bits of the waveform output mode register (bits 5 and 4 at address a6 16 ) select the type of pulse width modulation from the following: (1) when the pulse width modulation timer select bits = 00 , the common modulation to six of rtp1 1 , rtp1 0 , rtp0 3 , rtp0 2 , rtp0 1 , rtp0 0 is selected. for this modulation, since timer a1 is necessary, be sure to actuate this timer in the pulse width modu- lation mode. (2) when the pulse width modulation timer select bits = 01 , the modulation to the following two groups is selected; one consists of rtp1 1 , rtp1 0 , rtp0 3 , and the other consists of rtp0 2 , rtp0 1 , rtp0 0 . for this modulation, since timers a1 and a2 are necessary, be sure to actuate these timers in the pulse width modulation mode. (3) when the pulse width modulation timer select bits = 10 , the modulation to the following three groups is selected; one consists of rtp1 1 , rtp1 0 , and another consists of rtp0 3 , rtp0 2 , and the other consists of rtp0 1 , rtp0 0 . for this modulation, since timers a1, a2, and a4 are necessary, be sure to actuate these timers in the pulse width modulation mode. additionally, at this time, be sure to set the corresponding pulse width modulation enable bit of the three-phase output data register 1 (bits 2 through 0 at address a9 16 ) to 1 in order to enable the pulse width modulation. the other operations are the same as that of pulse mode 0. figure 53 shows example waveforms in pulse mode 1. in ports selecting pulse mode 1, output of rtp1 3 and rtp1 2 is con- trolled by the waveform output control bit 0 (bit 6) of the waveform output mode register; output of rtp1 1, rtp1 0 , rtp0 3 , rtp0 2 , rtp0 1 and rtp0 0 is done by the waveform output control bit 1 (bit 7). when setting the waveform output control bit to 1 , waveform is out- put from the corresponding port. when clearing that bit to 0 , wave- form output from the corresponding port stops, and the port becomes floating. these waveform output control bits 0, 1 are cleared to 0 by reset, by inputting a falling edge to pin p6out cut , or by executing instructions.
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 48 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers fig. 52 example waveforms in pulse mode 0 fig. 53 example waveforms in pulse mode 1 pulse output port example pulse output port example in the case of pulse output polarity select bit = 1 example of pulse width modulation for above pulse output port using timer a1 signal output each time timer a0 becames 0000 16 rtp0 3 rtp0 2 rtp0 0 rtp0 1 signal output each time timer a0 becames 0000 16 rtp0 3 rtp0 2 rtp0 0 rtp0 1 signal output each time timer a3 becames 0000 16 rtp1 0 rtp1 1 pulse output port example example of pulse width modulation for above pulse output port using timer a1 signal output each time timer a0 becames 0000 16 rtp1 1 rtp0 1 rtp1 0 rtp0 0 rtp0 2 rtp0 3 signal output each time timer a0 becames 0000 16 rtp1 1 rtp0 1 rtp1 0 rtp0 0 rtp0 2 rtp0 3
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 49 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers pulse output port mode 1 figure 54 shows the block diagram in the pulse output port mode 1. this mode has an 8-bit pulse output port. the waveform output se- lect bits (bits 0 to 2) of the pulse output control register (address a0 16 ) select use of pulse output the port. the 8-bit pulse output port can also be divided into ? bits and 4 bits?or ? bits and 2 bits? with the pulse output mode select bit (bit 3) of the pulse output control register (address a0 16 ); each of them can be individually controlled. set timers a8 and a5 to the timer mode because they are used in the pulse output port mode 1. figure 56 shows the bit configuration of timer a8 and a5 mode registers in the pulse output port mode 1. timers a8 and a5 start count when setting the corresponding timer count start bit to ?? and they stop it when clearing that bit to ?? fig. 54 block diagram in pulse output port mode 1 each bit using timer a5 as a trigger can also be controlled by an in- put trigger from pin rtp trg1 . this control is selected by the pulse output trigger select bits of the pulse output data register 0 (bits 7 and 6 at address a2 16 ). also, this externally-input trigger can be se- lected from the following three types: falling edges, rising edges, and falling and rising edges. the reversed content of the pulse output data bit can be output to each pulse output port by the pulse output polarity select bit of the pulse output data register 1 (bit 3 at address a4 16 ). when the pulse output polarity select bit = ?? the content of the pulse output data bit is output as it is; when the pulse output polarity select bit = ?? the reversed content is output. b0 b1 b2 b0 b1 b2 b3 b4 b5 rtp3 0 rtp3 1 rtp2 3 d q d q d q d q d q t d q rtp2 1 rtp2 2 d q r t d q d q d q r rtp2 0 t d q b6 b7 d q d q t rtp3 2 rtp3 3 p4out cut pulse output polarity select bit (bit 3 at address a4 16 ) waveform output control bit 0 (bit 6 at address a0 16 ) reset pulse width modulation circuit pulse output trigger select bits (bits 7, 6 at address a2 16 ) pulse width modulation output of timer a6 pulse width modulation timer select bits (bits 5, 4 at address a0 16 ) pulse width modulation output of timer a7 pulse width modulation output of timer a9 timer a8 pulse width modulation enable bits 0 through 2 (bits 0 through 2 at address a4 16 ) timer a5 rtp trg1 bits 0 through 3 of pulse output data register 0 (address a2 16 ) bits 4, 5 of three-phase output data register 0 (address a2 or 16 ) bits 4, 5 of three-phase output data register 1 (address a4 16 ) bits 6, 7 of pulse output data register 1 (address a4 16 ) data bus (even-numbered) pulse output mode select bit (bit 3 at address a0 16 ) waveform output control bit 1 (bit 7 at address a0 16 ) reset
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 50 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers fig. 55 bit configuration of pulse output control register in pulse output port mode 1 fig. 56 bit configuration of timer a8 and a5 mode registers in pulse output port mode 1 waveform output select bits 000 : parallel ports 001 : when pulse mode 0 is selected, rtp2 is selected. when pulse mode 1 is selected, rtp2, rtp3 1 , rtp3 0 are selected. 010 : when pulse mode 0 is selected, rtp3 is selected. when pulse mode 1 is selected, rtp3 3 and rtp3 2 are selected. 011 : when pulse mode 0 is selected, rtp2 and rtp3 are selected. when pulse mode 1 is selected, rtp2, rtp3 1 , rtp3 0 and rtp3 3 , rtp3 2 are selected. pulse output mode select bit 0 : pulse mode 0 1 : pulse mode 1 pulse width modulation timer select bits 0 0 : when pulse mode 0 is selected (valid only for rtp2), pulse width modulation by timer a6 when pulse mode 1 is selected (valid only for rtp2, rtp3 1 , rtp3 0 ), pulse width modulation by timer a6 0 1 : when pulse mode 0 is selected, do not set. when pulse mode 1 is selected (valid only for rtp2, rtp3 1 , rtp3 0 ), pulse width modulation by timer a6 ; rtp2 2 , rtp2 1 , rtp2 0 pulse width modulation by timer a7 ; rtp2 3 , rtp3 1 , rtp3 0 1 0 : when pulse mode 0 is selected, do not set. when pulse mode 1 is selected (valid only for rtp2, rtp3 1 , rtp3 0 ), pulse width modulation by timer a6 ; rtp2 1 , rtp2 0 pulse width modulation by timer a7 ; rtp2 3 , rtp2 2 pulse width modulation by timer a9 ; rtp3 1 , rtp3 0 1 1 : do not select. waveform output control bit 0 when pulse mode 0 is selected, 0 : rtp3 waveform outputs is disabled. 1 : rtp3 waveform outputs is enabled. when pulse mode 1 is selected, 0 : rtp3 3 , rtp3 2 waveform outputs are disabled. 1 : rtp3 3 , rtp3 2 waveform outputs are enabled. waveform output control bit 1 when pulse mode 0 is selected, 0 : rtp2 waveform output is disabled. 1 : rtp2 waveform output is enabled. when pulse mode 1 is selected, 0 : rtp2, rtp3 1 , rtp3 0 waveform outputs are disabled. 1 : rtp2, rtp3 1 , rtp3 0 waveform outputs are enabled. 76543210 address pulse output control register a0 16 timer a5 mode register d6 16 timer a8 mode register d9 16 fix these bits to 000000 in pulse output port mode. clock source select bits (see table 7.) 76543210 0 0 0 0 0 0 address
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 51 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers fig. 57 bit configuration of pulse output data registers 1 and 0 in pulse output port mode 1 pulse mode 0 this mode divides a pulse output port into 4 bits and 4 bits and indi- vidually controls them. when setting the pulse output mode select bit to 0 , and setting bits 2 and 1 to 0 and bit 0 to 1 of the waveform output select bits, four of rtp2 3 , rtp2 2 , rtp2 1 , and rtp2 0 become the pulse output ports (rtp2 selected). when setting the pulse output mode select bit to 0 , and setting bits 2 and 0 to 0 and bit 1 to 1 of the waveform output select bits, four of rtp3 3, rtp3 2, rtp3 1 , rtp3 0 become the pulse output ports (rtp3 selected). when setting the pulse output mode select bit to 0 , and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits, the following two groups become the pulse output ports: four of rtp3 3 , rtp3 2 , rtp3 1 , rtp3 0 four of rtp2 3 , rtp2 2 , rtp2 1 , rtp2 0 . each time the contents of timer a8 counter become 0000 16 , the con- tents of the pulse output data register 1 (address a4 16 ) s high-order 4 bits (bits 7 to 4), which corresponding to rtp3 3 , rtp3 2, rtp3 1 , rtp3 0 , are output from ports. each time the contents of timer a5 counter become 0000 16 , the con- tents of pulse output data register 0 (address a2 16 ) s low-order 4 bits (bits 3 to 0), which corresponding to rtp2 3 , rtp2 2 , rtp2 1 , rtp2 0 , are output from ports. when writing 0 to the specified one of the pulse output data bits, l level is output from the pulse output port when the contents of the corresponding timer counter become 0000 16 ; when writing 1 to it, h level is output from the pulse output port. in the case that an input trigger of pin rtp trg1 is selected, the data written to the pulse output data bit is output from the corresponding pulse output port by this selected trigger. additionally, pulse width modulation can be applied for rtp2 3 , rtp2 2 , rtp2 1 , and rtp2 0 . because timer a6 is used for pulse width modulation, actuate timer a6 in the pulse width modulation mode. when any of pulse output data bits is 1 , the pulse to which pulse width modulation has been applied is output from the pulse output port when the contents of timer a5 counter become 0000 16 . the pulse width modulation using timer a6 can be applied by setting the pulse width modulation enable bit 0 of the pulse output data reg- ister 1 (bit 0 at address a4 16 ) to 1 and the pulse width modulation timer select bits of the pulse output control register (bits 5 and 4 at address a0 16 ) to 00 . figure 58 shows example waveforms in pulse mode 0. in ports selecting pulse mode 0, output of rtp3 3 , rtp3 2 , rtp3 1 and rtp3 0 is controlled by the waveform output control bit 0 (bit 6) of pulse output control register; output of rtp2 3 , rtp2 2 , rtp2 1 and rtp2 0 is done by the waveform output control bit 1 (bit 7). when setting the waveform output control bit to 1 , waveform is out- put from the corresponding port. when clearing that bit to 0 , wave- form output from the corresponding port stops, and the port becomes floating. the waveform output control bits are cleared to 0 by reset or by executing instructions. also, the waveform output control bit 1 can be cleared to 0 by in- putting a falling edge to pin p4out cut . rtp2 0 pulse output data bit rtp2 1 pulse output data bit rtp2 2 pulse output data bit rtp2 3 pulse output data bit rtp3 0 pulse output data bit; valid when pulse mode 1 is selected. rtp3 1 pulse output data bit; valid when pulse mode 1 is selected. pulse output trigger select bits 0 0 : underflow of timer a5 0 1 : falling edge of input signal to pin rtp trg1 1 0 : rising edge of input signal to pin rtp trg1 1 1 : falling and rising edges of input signal to pin rtp trg1 76543210 address pulse output data register 1 76543210 address pulse output data register 0 a4 16 a2 16 pulse width modulation enable bit 0 0 : no pulse width modulation by timer a6 1 : pulse width modulation by timer a6 pulse width modulation enable bit 1 0 : no pulse width modulation by timer a7 1 : pulse width modulation by timer a7 pulse width modulation enable bit 2 0 : no pulse width modulation by timer a9 1 : pulse width modulation by timer a9 pulse output polarity select bit 0 : positive 1 : negative rtp3 0 pulse output data bit; valid when pulse mode 0 is selected. rtp3 1 pulse output data bit; valid when pulse mode 0 is selected. rtp3 2 pulse output data bit rtp3 3 pulse output data bit
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 52 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers pulse mode 1 this mode divides a pules output port into 6 bits and 2 bits and indi- vidually control them. when setting the pulse output mode select bit to 1 , and setting bits 2 and 1 to 0 and bit 0 to 1 of the waveform output select bits, the following become the pulse output ports: six of rtp3 1 , rtp3 0 , rtp2 3 , rtp2 2 , rtp2 1 , rtp2 0 when setting the pulse output mode select bit to 1 , and setting bits 2 and 0 to 0 and bits 1 to 1 of the waveform output select bits, two of rtp3 3, rtp3 2 become the pulse output ports. when setting the pulse output mode select bit to 1 , and setting bit 2 to 0 and bits 1 and 0 to 1 of the waveform output select bits, the following two groups become the pulse output ports: two of rtp3 3 , rtp3 2 six of rtp3 1 , rtp3 0 , rtp2 3 , rtp2 2 , rtp2 1 , rtp2 0 each time the contents of timer a8 counter become 0000 16, the con- tents of pulse output data register 1 (address a4 16 ) s bits 7 and 6, which corresponding to rtp3 3 and rtp3 2 , are output from ports. each time the contents of timer a5 counter become 0000 16, the con- tents of pulse output data register 0 (address a2 16 ) s low-order 6 bits (bits 5 to 0), which corresponding to rtp3 1 , rtp3 0 , rtp2 3, rtp2 2, rtp2 1, rtp2 0, are output from ports. whether to control these pulse output ports by an underflow of timer a5 or an input edge to pin rtp trg1 is selected by the pulse output trigger select bit of the pulse output data register 0 (bits 7 and 6 at address a2 16 ). additionally, pulse width modulation can be applied to rtp3 1, rtp3 0, rtp2 3, rtp2 2, rtp2 1, and rtp2 0 . the pulse width modula- tion timer select bits of the pulse output control register (bits 5 and 4 at address a0 16 ) select the type of pulse width modulation from the following: (1) when the pulse width modulation timer select bits = 00 , the common modulation to six of rtp3 1 , rtp3 0 , rtp2 3 , rtp2 2 , rtp2 1 , rtp2 0 is selected. for this modulation, since timer a6 is necessary, be sure to actuate this timer in the pulse width modu- lation mode. (2) when the pulse width modulation timer select bits = 01 , the modulation to the following two groups is selected; one consists of rtp3 1 , rtp3 0 , rtp2 3 , and the other consists of rtp2 2 , rtp2 1 , rtp2 0 . for this modulation, since timers a6 and a7 are necessary, be sure to actuate these timers in the pulse width modulation mode. (3) when the pulse width modulation timer select bits = 10 , the modulation to the following three groups is selected; one consists of rtp3 1 , rtp3 0 , and another consists of rtp2 3 , rtp2 2 , and the other consists of rtp2 1 , rtp2 0 . for this modulation, since timers a6, a7, and a9 are necessary, be sure to actuate these timers in the pulse width modulation mode. additionally, at this time, be sure to set the corresponding pulse width modulation enable bit of the pulse output data register 1 (bits 2 through 0 at address a4 16 ) to 1 in order to enable the pulse width modulation. the other operations are the same as that of pulse mode 0. figure 59 shows example waveforms in pulse mode 1. in ports selecting pulse mode 1, output of rtp3 3 and rtp3 2 is con- trolled by the waveform output control bit 0 (bit 6) of the pulse output control register; output of rtp3 1, rtp3 0 , rtp2 3 , rtp2 2 , rtp2 1, and rtp2 0 is done by the waveform output control bit 1 (bit 7). when setting the waveform output control bit to 1 , waveform is out- put from the corresponding port. when clearing that bit to 0 , wave- form output from the corresponding port stops, and the port becomes floating. these waveform output control bits 0, 1 are cleared to 0 by reset, by inputting a falling edge to pin p4out cut , or by executing instructions.
preliminar y notice: this is not a final specification. some parametric limits are subject to change. 53 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp 16-bit cmos microcomputer mitsubishi microcomputers fig. 58 example waveforms in pulse mode 0 fig. 59 example waveforms in pulse mode 1 pulse output port example pulse output port example in the case of pulse output polarity select bit = 1 example of pulse width modulation for above pulse output port using timer a6 signal output each time timer a5 becames 0000 16 rtp2 3 rtp2 2 rtp2 0 rtp2 1 signal output each time timer a5 becames 0000 16 rtp2 3 rtp2 2 rtp2 0 rtp2 1 signal output each time timer a8 becames 0000 16 rtp3 0 rtp3 1 pulse output port example example of pulse width modulation for above pulse output port using timer a6 signal output each time timer a5 becames 0000 16 rtp3 1 rtp2 1 rtp3 0 rtp2 0 rtp2 2 rtp2 3 signal output each time timer a5 becames 0000 16 rtp3 1 rtp2 1 rtp3 0 rtp2 0 rtp2 2 rtp2 3
54 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers serial i/o ports two independent serial i/o ports are provided. figure 60 shows a block diagram of the serial i/o ports. bits 0 through 2 of the uarti(i = 0, 1, 2) transmit/receive mode reg- ister shown in figure 61 are used to determine whether to use ports p1 and p8 as programmable i/o ports, clock synchronous serial i/o ports, or asynchronous (uart) serial i/o ports which use start and stop bits. figures 62 and 63 show the block diagrams of the receiver/transmit- ter. figure 64 shows the bit configuration of the uarti transmit/receive control register. each communication method is described below. fig. 61 bit configuration of uarti transmit/receive mode register fig. 60 block diagram of serial i/o port uarti receive register t x d i r x d i receive control circuit transmit control circuit uarti transmit register 1/16 divider 1/2 divider 1/(n + 1) divider 1/16 divider transfer clock transfer clock uarti transmit buffer register uart clock synchronous clock synchronous clock synchronous (when internal clock selected) brg count source select bits f 2 f 16 f 64 f 512 clock synchronous (internal clock) uart d 7 d 6 d 5 d 4 d 3 d 2 d 1 uarti receive buffer register d 0 d 7 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0d 8 0 0 0 0 0 0 brgi uart0 (addresses 33 16 , 32 16 ) uart1 (addresses 3b 16 , 3a 16 ) uart2 (addresses b3 16 , b2 16 ) uart0 (addresses 37 16, 36 16 ) uart1 (addresses 3f 16 , 3e 16 ) uart2 (addresses b7 16 , b6 16 ) cts i /rts i clock synchronous (external clock) n = a value set into the uarti baud rate register (brgi) clk i cts i cts i /clk i data bus (even) data bus (odd) bit converter data bus (odd) data bus (even) bit converter serial i/o mode select bits 0 0 0 : serial i/o is invalid. (ports p1 and p8 function as programmable i/o ports.) 0 0 1 : clock synchronous 1 0 0 : 7-bit uart 1 0 1 : 8-bit uart 1 1 0 : 9-bit uart internal/external clock select bit 0 : internal clock 1 : external clock stop bit length select bit (valid in uart mode.) 0 : 1 stop bit 1 : 2 stop bits odd/even parity select bit (valid in uart mode with the parity enable bit = ??) (note) 0 : odd parity 1 : even parity parity enable bit (valid in uart mode) (note) 0 : no parity 1 : with parity sleep select bit (valid in uart mode) (note) 0 : no sleep 1 : sleep 76543210 uart 0 transmit/receive mode register uart 1 transmit/receive mode register uart 2 transmit/receive mode register addresses 30 16 38 16 b0 16 note: in the clock synchronous serial i/o mode, bits 4 to 6 are invalid. (each of them may be 0 or 1 .) furthermore, fix bit 7 to 0 .
55 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers data bus (odd) data bus (even) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp sp par no parity uarti receive register r x d i uarti receive buffer register 9-bit uart 7-bit uart 7-bit uart 8-bit uart synchronous uart 8-bit uart 9-bit uart synchronous synchronous parity 2sp 1sp 0 0 0 0 0 0 0 sp : stop bit par : parity bit fig. 62 block diagram of receiver fig. 63 block diagram of transmitter d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 sp par t x d i 2sp sp 1sp uart ? data bus (odd) data bus (even) no parity 7-bit uart 9-bit uart synchronous 7-bit uart 8-bit uart 9-bit uart synchronous 8-bit uart synchronous parity sp : stop bit par : parity bit uarti transmit register uarti receive transmit register
56 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 64 bit configuration of uarti transmit/receive control register /lsb msb t x epty 76543210 r/c cs 1 cs 0 brg count source select bits 0 0 : f 2 0 1 : f 16 1 0 : f 64 1 1 : f 512 cts/rts function select bit (note 1) 0 : cts function is selected. 1 : rts function is selected. transmit register empty flag 0 : data is present in the transmit register. (transmission is in progress.) 1 : no data is present in the transmit register. (transmission is completed.) cts/rts enable bit 0 : cts, rts function is enabled. 1 : cts, rts function is disabled. uarti receive interrupt mode select bit 0 : reception interrupt 1 : reception error interrupt clk polarity select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) 0 : at the falling edge of a transfer clock, transmit data is output; at the rising edge, receive data is input. when not in transfer, pin clk? level is ?? 1 : at the rising edge of a transfer clock, transmit data is output; at the falling edge, receive data is input. when not in transfer, pin clk? level is ?? transfer format select bit (this bit is used in the clock synchronous serial i/o mode.) (note 2) 0 : lsb (least significant bit) first 1 : msb (most significant bit) first 76543210 re ri oer fer per sum ti te transmit enable bit transmit buffer empty flag receive enable bit receive complete flag overrun error flag framing error flag (note 3) parity error flag (note 3) error sum flag (note 3) uart0 transmit/receive control register 0 uart1 transmit/receive control register 0 uart2 transmit/receive control register 0 address 34 16 3c 16 b4 16 uart0 transmit/receive control register 1 uart1 transmit/receive control register 1 uart2 transmit/receive control register 1 address 35 16 3d 16 b5 16 cpl notes 1: valid when the cts/rts enable bit (bit 4) = ?? 2: fix these bits to ??in uart mode or when serial i/o is invalid. 3: valid in uart mode.
57 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers clock synchronous serial communi- cation a case where communication is performed between two clock syn- chronous serial i/o ports as shown in figure 65 will be described. (the transmission side will be denoted by subscript j and the receiv- ing side will be denoted by subscript k.) bit 0 of the uartj transmit/receive mode register and uartk trans- mit/receive mode register must be set to ??and bits 1 and 2 must be ?? the length of the transmission data is fixed at 8 bits. bit 3 of the uartj transmit/receive mode register of the clock send- ing side is cleared to ??to select the internal clock. bit 3 of the uartk transmit/receive mode register of the clock receiving side is set to ??to select the external clock. bits 4, 5 and 6 are ignored in clock synchronous mode. bit 7 must always be ?? the clock source is selected by bit 0 (cs 0 ) and bit 1 (cs 1 ) of the clock-sending-side uartj transmit/receive control register 0. as shown in figure 60, the selected clock is divided by (n + 1), then by 2, is passed through a transmission control circuit, and is output as transmission clock clk j . therefore, when the selected clock is fi, bit rate = f i / {(n + 1) 2} on the clock receiving side, the cs 0 and cs 1 bits of the uartk transmit/receive control register 0 are ignored because an external clock is selected. both of uart0 and uart1 can use cts and rts functions. bit 4 of the uarti transmit/receive control register 0 is used to de- termine whether to use cts or rts signal. bit 4 must be ??when cts or rts signal is used. bit 4 must be ??when cts and rts sig- nals are not used. when cts and rts signals are not used, cts/ rts pin can be used as a normal port pin. when using pin cts/rts, : ?if bit 2 of the uarti transmit/receive control register 0 is cleared to ?? cts input is selected. ?if bit 2 is set to ?? rts output is selected. the case using cts and rts signals are explained below. as shown in figure 72, bits 2, 3 and 5 of the serial i/o pin control regis- ter can determine whether port pins p1 3, p1 7 and p8 3 are used as pins t x d i or as port pins. when bits 2, 3 and 5 are ?? p1 3, p1 7 and p8 3 function as pins t x d i ; when bits 2, 3 and 5 are ?? p1 3, p1 7 and p8 3 function as port pins. therefore, in the input-only system where pins t x d i are not used, pins t x d i can function as port pins. fig. 65 clock synchronous serial communication uartj transmit register t x d j r x d j clk j cts j uartj transmit buffer register uartj receive buffer register uartj receive register uartj transmit/receive mode register uartj transmit/receive control register 0 uartj transmit/receive control register 1 000 0 t x epty cs 1 cs 0 re ri oer fer per cpl cpl sum ti te 0 uartk transmit register uartk transmit buffer register uartk receive buffer register uartk receive register uartk transmit/receive mode register uartk transmit/receive control register 0 uartk transmit/receive control register 1 011 0 1 t x epty msb /lsb re ri oer fer per sum ti te 0 1 t x d k r x d k clk k rts k msb /lsb
58 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers transmission transmission is started when bit 0 (tej flag: transmit enable bit) of uartj transmit/receive control register 1 is 1 , bit 1 (tij flag) of one is 0 , and cts j input is l . the tij flag indicates whether the trans- mit buffer register is empty or not. it is cleared to 0 when data is written in the transmit buffer register; it is set to 1 when the contents of the transmit buffer register is transferred to the transmit register and the transmit buffer register becomes empty. when all of the transmit conditions are satisfied, the transmit data in the transmit buffer register are transferred to the transmit register, and transmission starts. as shown in figure 66, data is output from t x d j pin each time when transmission clock clk j changes from h to l . (in the clock synchronous serial i/o mode, the polarity of a transfer clock can be changed. for details, refer to the section on the selection of the transfer clock polarity.) the data is output from the least significant bit. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmission start condition is satisfied. the next transmission is performed succeedingly. once transmission has started, the tej flag, tij flag, and cts j signals are ignored until data transmission completes. therefore, transmission is not interrupted when cts j input is changed to h during transmission. the transmission start condition indicated by tej flag, tij flag, and cts j is checked while the t end j signal (shown in figure 66) is h . therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tij flag is cleared to 0 before thet end j signal goes h . bit 3 (t x eptyj flag) of uartj transmit/receive control register 0 changes to 1 at the next cycle just after the t end j signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission has completed. when the tij flag changes from 0 to 1 , the interrupt request bit in the uartj transmit interrupt control register is set to 1 . receive when bit 2 (rek flag) of the uart k transmit/receive control register 1 is set to 1 , reception becomes enabled. in this case, when the clkk signal is input, the receive operation starts simultaneously with this signal. the rts k output is h when the rek flag is 0 . when the rek flag is set to 1 , the rts k output becomes l . this informs the transmit- ter side that reception becomes enabled. when the receive opera- tion starts, the rts k output automatically becomes h . when the receive operation starts, the receiver takes data from pin rxdk each time when the transmit clock (clk j ) turns from l to h . simultaneously with reception, the contents of the receiver register is shifted bit by bit. (note that, in the clock synchronous serial communication, the polar- ity of a transfer clock can be inverted. for details, refer to the section on the polarity of the transfer clock.) when an 8-bit data is received, the contents of the receive register is transferred to the receive buffer register and bit 3 (rik flag) of uartk transmit/receive control regis- ter 1 is set to 1 . in other words, the setting 1 to the rik flag indi- cates that the receive buffer register contains the received data. at this time, if the low-order byte of the uartk receive buffer register is read out, the rts k output turns back to l . this indicates that the next data reception becomes enabled. bit 4 (oerk flag) of uartk transmit/receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while rik flag is 1 , and indicates that the next data was transferred to the receive register before the contents of the receive buffer regis- ter was read. (in other words, this indicates that an overrun error has occurred.) rik flag is automatically cleared to 0 when the low-order byte of the receive buffer register is read or when the rek flag is cleared to 0 . the oerk flag is cleared when the rek flag is cleared. bit 5 (ferk flag), bit 6 (perk flag), and bit 7 (sumk flag) are ignored in clock synchronous mode. as shown in figure 60, with clock synchronous serial communica- tion, data cannot be received unless the transmitter is operating be- cause the receive clock is created from the transmission clock. therefore, the transmitter must be operating even when there is no need to sent data from uartk to uartj.
59 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 66 clock synchronous serial i/o timing interrupt request at completion of reception when the rik flag changes from 0 to 1 , in other words, when the receive operation is completed, the interrupt request bit of the uartk receive interrupt control register can be set to 1 . the timing when this interrupt request bit is to be set to 1 can be selected from the following: each reception when an error occurs at reception if bit 5 of the uartk transmit/receive control register 0 (uart re- ceive interrupt mode select bit) is cleared to 0 , the interrupt request bit is set to 1 at each reception. if bit 5 is set to 1 , the interrupt re- quest bit is set to 1 only when an error occurs. (in the clock syn- chronous serial communication, only when an overrun error occurs, the interrupt request bit is set to 1 .) polarity of transfer clock in the clock synchronous serial communication, by bit 6 of the uartj transmit/receive control register 0 (cpl), the polarity of a transfer clock can be selected. as shown in figure 67, when bit 6 = 0 , the polarity is as follows: in transmission, transmit data is output at the falling edge of clk j . in reception, receive data is input at the rising edge of clk k . when not in transfer, clk i is at h level. when bit 6 = 1 , the polarity is as follows: in transmission, transmit data is output at the rising edge of clk j . in reception, receive data is input at the rising edge of clk k . when not in transfer, clk i is at l level. transmission clock te j 1/f i + + 0 clk j t endj t x d j t x epty j
60 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 67 polarity of transfer clock ? s level is h . ? s level is l .
61 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers selection of transfer format in clock synchronous serial communication, transfer format can be selected by bit 7 of the transmit/receive control register 0. when bit 7 is 0 , transfer format is lsb first. when bit 7 is 1 , transfer format is msb first. this function is realized by changing connection relation between the transmit buffer register and the receive buffer register when writ- ing transmit data to the transmit buffer register or reading receive data from the receive buffer register. accordingly, the transmitter s operation is the same in both transfer formats. figure 68 shows the connection relation. fig. 68 connection relation between transmit buffer register, receive buffer register, and data bus bit 7 in transmit/receive control register 0 write to transmit buffer register read from receive buffer register 0 (lsb first) 1 (msb first) transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 transmit buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 receive buffer register db 7 data bus d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 db 6 db 5 db 4 db 3 db 2 db 1 db 0 precautions for clock synchronous serial communication in the clock synchronous serial communication, the separate func- tion for cts i /rts i cannot be selected. furthermore, when an inter- nal clock is selected, rts output is undefined. therefore, do not use the rts function. before transmit operation is performed, be sure to clear bits 2, 3 and 5 of the serial i/o pin control register (address ac 16 ) to 00 .
62 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 69 transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit selected fig. 70 transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits selected asynchronous serial communication asynchronous serial communication can be performed using 7-, 8-, or 9-bit length data. the operation is the same for all data lengths. the following is the description for 8-bit asynchronous communication. with 8-bit asynchronous communication, bit 0 of uarti transmit/re- ceive mode register is 1 , bit 1 is 0 , and bit 2 is 1 . bit 3 is used to select an internal clock or an external clock. if bit 3 is 0 , an internal clock is selected and if bit 3 is 1 , then external clock is selected. if an internal clock is selected, bit 0 (cs 0 ) and bit 1 (cs 1 ) of uarti transmit/receive control register 0 are used to select the clock source. when an internal clock is selected for asynchronous serial communication, the clk i pin can be used as a normal i/o pin. the selected internal or external clock is divided by (n + 1), then by 16, and is passed through a control circuit to create the uart trans- mission clock or uart receive clock. therefore, the transmission speed can be changed by changing the contents (n) of the bit rate generator. if the selected clock is an inter- nal clock pfi or an external clock f ext , bit rate = (fi or f ext ) / {(n+1) 1 , the above separation is performed. when each of bits 0, 1 and 4 = 0 , no sepa- ration is performed. table 8 lists the selection methods of the cts/rts function. (1/f i or 1/f ext ) +
63 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers succeedingly. once transmission has started, the tei flag, tii flag, and ctsi signal are ignored until data transmission is completed. therefore, transmission does not stop until it completes event if, dur- ing transmission, the tei flag is cleared to 0 or ctsi input is set to 1 . the transmission start condition indicated by tei flag, tii flag, and ctsi is checked while the t end i signal shown in figure 69 is h . therefore, data can be transmitted continuously if the next transmis- sion data is written in the transmit buffer register and tii flag is cleared to 0 before the t end i signal goes h . bit 3 (t x eptyi flag) of uarti transmit/receive control register 0 changes to 1 at the next cycle just after the t end i signal goes h and changes to 0 when transmission starts. therefore, this flag can be used to determine whether data transmission is completed. when the tii flag changes from 0 to 1 , the interrupt request bit of the uarti transmit interrupt control register is set to 1 . transmission transmission is started when bit 0 (tei flag transmit enable flag) of uarti transmit/receive control register 1 is 1 , bit 1 (tii flag) is 0 , and cts i input (in other words, transmit enable signal input from re- ceiver) is l . the tii flag indicates whether the transmit buffer is empty or not. it is cleared to 0 when data is written in the transmit buffer; it is set to 1 when the contents of the transmit buffer register is transferred to the transmit register. when all of the transmission conditions are satisfied, transmit data is transferred to the transmit register, and transmit operation starts. as shown in figures 69 and 70, data is output from the t x di pin with the stop bit or parity bit specified by bits 4 through 6 of uarti trans- mit/receive mode register. the data is output from the least signifi- cant bit. when the transmit register becomes empty after the contents has been transmitted, data is transferred automatically from the transmit buffer register to the transmit register if the next transmit start condi- tion is satisfied. then, the next transmission is performed fig. 71 receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit selected start bit stop bit start bit d 0 d 1 d 7 check to be l level starting at the falling edge of start bit data fetched f i or f ext re i r x d i receive clock ri i rts i
64 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers table 8. selection methods of cts/rts function cts i /rts i separate select bit ? ? ? ? receive receive is enabled when bit 2 (rei flag) of uarti transmit/receive control register 1 is set to 1. as shown in figure 71, the frequency divider circuit (1/16) at the receiving side begin to work when a start bit arrives and the data is received. if rtsi output is selected by setting bit 2 of uarti transmit/receive control register 0 to 1 , the rtsi output is h when the rei flag is 0 . when the rei flag changes to 1 , the rtsi output goes l to inform the receiver that reception has become enabled. when the receive operation starts, the rtsi output automatically becomes h . the entire transmission data bits are received when the start bit passes the final bit of the receive block shown in figure 62. at this point, the contents of the receive register is transferred to the receive buffer register and bit 3 (rli flag) of uarti transmit/receive control register 1 is set to 1. in other words, the rii flag indicates that the receive buffer register contains data when it is set to 1. at this time, when the low-order byte of the uartk receive buffer register is read out, rtsi output goes back to l to indicate that the register is ready to receive the next data. bit 4 (oeri flag) of uarti transmit/receive control register 1 is set to 1 when the next data is transferred from the receive register to the receive buffer register while the rii flag is 1 , in other words, when an overrun error occurs. if the oeri flag is 1 , it indicates that the next data has been transferred to the receive buffer register before the contents of the receive buffer register has been read. bit 5 (feri flag) is set to 1 when the number of stop bits is less than required (framing error). bit 6 (peri flag) is set to 1 when a parity error occurs. bit 7 (sumi flag) is set to 1 when either the oeri flag, feri flag, or the peri flag is set to 1. therefore, the sumi flag can be used to determine whether there is an error. the setting of the rii flag, oeri flag, feri flag, and the peri flag is performed while transferring the contents of the receive register to the receive buffer register. cts 0 /rts 0 separate select bit 0 : cts 0 /rts 0 are used together. 1 : cts 0 /rts 0 are separated. cts 1 /rts 1 separate select bit 0 : cts 1 /rts 1 are used together. 1 : cts 1 /rts 1 are separated. txd 0 /p1 3 switch bit 0 : functions as txd 0. 1 : functions as p1 3. txd 1 /p1 7 switch bit 0 : functions as txd 1. 1 : functions as p1 7. cts 2 /rts 2 separate select bit 0 : cts 2 /rts 2 are used together. 1 : cts 2 /rts 2 are separated. txd 2 /p8 3 switch bit 0 : functions as txd 2. 1 : functions as p8 3. 76543210 serial i/o pin control register address ac 16
65 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers the feri, peri, and sumi flags are cleared to 0 when reading the low-order byte of the receive buffer register or when writing 0 to the rei flag. the oeri flag is cleared to 0 when writing 0 to the rei flag. interrupt request at completion of reception when the rik flag changes from 0 to 1 , in other words, when the receive operation is completed, the interrupt request bit of the uartk receive interrupt control register can be set to 1 . the timing when this interrupt request bit is to be set to 1 can be selected from the following: each reception when an error occurs at reception if bit 5 of the uartk transmit/receive control register 0 (uart re- ceive interrupt mode select bit) is cleared to 0 , the interrupt request bit is set to 1 at each reception. if bit 5 is set to 1 , the interrupt request bit is set to 1 only when an error occurs. (in the clock asyn- chronous serial communication, when an overrun error, framing er- ror, or parity error occurs, the interrupt request bit is set to 1 .) sleep mode the sleep mode is used to communicate only between certain micro- computers when multiple microcomputers are connected through serial i/o. the microcomputer enters the sleep mode when bit 7 of uarti transmit/receive mode register is set to 1 . the operation of the sleep mode for an 8-bit asynchronous commu- nication is described below. when sleep mode is selected, the contents of the receive register is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit asyn- chronous communication and bit 8 if 9-bit asynchronous communi- cation) of the received data is 0 . also the rii, oeri, feri, peri, and the sumi flags are unchanged. therefore, the interrupt request bit of the uarti receive interrupt control register is also unchanged. normal receive operation takes place when bit 7 of the received data is 1 . the following is an example of how the sleep mode can be used. the main microcomputer first sends data: bit 7 is 1 and bits 0 to 6 are set to the address of the subordinate microcomputer to be com- municated with. then all subordinate microcomputers receive this data. each subordinate microcomputer checks the received data, clears the sleep bit to 0 if bits 0 through 6 are its own address and sets the sleep bit to 1 if not. next, the main microcomputer sends data with bit 7 cleared. then the microcomputer which cleared the sleep bit will receive the data, but the microcomputers which set the sleep bit to 1 will not. in this way, the main microcomputer is able to communicate only with the designated microcomputer. precautions for clock asynchronous (uart) serial communication when ctsi and rtsi are separated, pin clki cannot be used. therefore, when ctsi and rtsi are separated in uart mode, be sure to select an internal clock. before transmit operation is performed, be sure to clear bits 2, 3 and 5 of the serial i/o pin control register (address ac 16 ) to 00 .
66 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers a-d converter the a-d converter is a 10-bit successive approximation converter. the use of a-d converter or the use of comparator can be selected for each a-d input pin. the contents of the comparator function se- lect register specify it. figure 73 shows a block diagram of the a-d converter. fig. 73 block diagram of a-d converter ad (1,1) f 2 (1,0) (0,1) (0,0) 1/2 1/2 f 1 av ss an 0 an 1 an 2 an 3 an 4 an 5 an 6 an 7 an 8 an 9 v ref v ref 1 0 1 an 10 an 11 resistor ladder network v ref connection select bit compa- rator a-d conversion frequency ( ad ) select bits 1, 0 selection of a-d conversion frequency v comparator function select register 1 comparator function select register 0 selector selector comparator result register 0 comparator result register 1 a-d control register 2 a-d control register 1 a-d control register 0 control circuit successive approximation register a-d register 0 a-d register 1 a-d register 2 a-d register 3 a-d register 4 a-d register 5 a-d register 6 a-d register 7 a-d register 8 a-d register 9 a-d register 10 a-d register 11 data bus (even) data bus (odd) selector decoder
67 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers figure 74 shows the bit configuration of the comparator function se- lect register 0 (address dc 16 ), and figure 75 shows that of the com- parator function select register 1 (address dd 16 ). each of bits 7 to 0 corresponds to its own channel, respectively. each channel can be selected as either an a-d converter or a comparator. when the bit is ?? the channel corresponding to it functions as a 10-bit or an 8-bit a-d converter. when the bit is ?? the channel functions as a com- parator. when selecting an a-d converter, an input voltage to a selected ana- log input pin is a-d converted and the result is stored into one of these a-d registers. when selecting a comparator, d-a conversion is performed to the value of which high-order 8 bits are the value stored in an even ad- dress of the a-d converter and of which low-order 2 bits are ?0 2 . then, this d-a converted value is compared with the voltage sup- plied to an analog input pin. after the comparison, when the voltage supplied to an analog input pin is higher, ??is stored into the com- parator result register 0 (address de 16 ) shown in figure 76, or the comparator result register 1 (address df 16 ) shown in figure 77. when it is lower, ??is stored into that of these register. be sure to perform only read to the a-d register of which channel is selected as an a-d converter, and perform only write to the a-d reg- ister of which channel is selected as a comparator. additionally, do not write to the comparator function select registers 0, 1 and the a-d register while an a-d converter or a comparator is operating. port direction registers bits corresponding to pins to be a-d con- verted must be ??(input mode) because analog input ports are mul- tiplexed with ports p7 and p8. figure 78 shows the bit configuration of the a-d control register 0 (address 1e 16 ), figure 79 shows that of the a-d control register 1 (address 1f 16 ), and figure 80 shows that of the a-d control register 2 (address db 16 ). the operation clock of the a-d converter, ad , is selected by the fol- lowing bits: bit 7 of the a-d control register 0 and bit 4 of the a-d con- trol register 1. when bit 4 of the a-d control register 1 = ?? ad is selected as fol- lows: ?if bit 7 of the a-d control register 0 = ?? ad = f 2 /4. ?if bit 7 of the a-d control register 0 = ?? ad = f 2 /2. when bit 4 of the a-d control register 1 = ?? ad is selected as fol- lows: ?if bit 7 of the a-d control register 0 = ?? ad = f 2 . ?if bit 7 of the a-d control register 0 = ?? ad = f 1 . note that the highest frequency, ad = f 1 , can be selected only in the 8-bit resolution mode. ad during a-d conversion must be 250 khz or more because the comparator uses a capacity coupling amplifier. bit 3 of a-d control register 1 is used to select whether to regard the conversion result as 10-bit or as 8-bit data. the conversion result is regarded as 10-bit data when bit 3 is ??and as 8-bit data when bit 3 is ?? when the conversion result is used as 10-bit data, the low-order 8 bits of the conversion result are stored in the even address of the corresponding a-d register and the high-order 2 bits are stored in bits 0 and 1 at the odd address of the corresponding a-d register. bits 2 to 7 of the a-d register odd address are ?00000 2 ?when read. when the conversion result is used as 8-bit data, the high-order 8 bits of the 10-bit a-d conversion result are stored in even address of the corresponding a-d register. in this case, the value at the a-d registers odd address is ?0 16 ?when read. whether to connect the reference voltage input (v ref ) with the lad- der network or not depends on bit 5 of the a-d control register 1. the v ref pin is connected when bit 5 is ??and is disconnected when bit 5 is ??(high impedance state). when a-d or d-a conversion is not performed, current from the v ref pin to the ladder network can be cut off by disconnecting ladder net- work from the v ref pin. before starting a-d conversion, wait for 1 s or more after clearing bit 5 to ??
68 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 76 bit configuration of comparator result register 0 fig. 77 bit configuration of comparator result register 1 fig. 74 bit configuration of comparator function select register 0 fig. 75 bit configuration of comparator function select register 1 76543210 0 : a-d converter is selected. 1 : comparator is selected. comparator function select register 0 an 0 pin comparator function select bit an 1 pin comparator function select bit an 2 pin comparator function select bit an 3 pin comparator function select bit an 4 pin comparator function select bit an 5 pin comparator function select bit an 6 pin comparator function select bit an 7 pin comparator function select bit address dc 16 76543210 0000 comparator function select register 1 an 8 pin comparator function select bit an 9 pin comparator function select bit an 10 pin comparator function select bit an 11 pin comparator function select bit fix these bits to ?000? a ddress dc 16 0 : a-d converter is selected. 1 : comparator is selected. 76543210 comparator result register 0 an 0 pin comparator result bit an 1 pin comparator result bit an 2 pin comparator result bit an 3 pin comparator result bit an 4 pin comparator result bit an 5 pin comparator result bit an 6 pin comparator result bit an 7 pin comparator result bit address de 16 note: do not access with the oram(oramb) or andm(andmb) instruction. 0 : ani input level is lower than set digital value 1 : ani input level is higher than set digital value 76543210 comparator result register 1 an 8 pin comparator result bit an 9 pin comparator result bit an 10 pin comparator result bit an 11 pin comparator result bit address de 16 note: do not access with the oram(oramb) or andm(andmb) instruction. 0 : ani input level is lower than set digital value 1 : ani input level is higher than set digital value
69 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y n otice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers operation mode the operation mode is selected by bits 3 and 4 of a-d control regis- ter 0 and bit 2 of a-d control register 1. the available operation modes are one-shot, repeat, single sweep, repeat sweep 0, and re- peat sweap 1. note that, as for pins an 8 through an 11 , only one-shot and repeat modes can be selected. either an a-d converter or a comparator can be selected respectively for each pin in the following 5 modes. the following description applies to the case where the bit of the comparator function select register 0/1 is 0 and an a-d con- verter is selected. it also applies to a comparator s operation except that an a-d conversion is changed to a comparator operation and the result of the comparison is stored into the comparator result reg- ister 0/1. (1) one-shot mode one-shot mode is selected when bits 3 and 4 of a-d control register 0 are 0 . the a-d conversion pins are selected with bits 0 to 2 of a-d control register 0 and bits 0 to 3 of a-d control register 2. a-d conversion or comparator operation is started when bit 6 of a-d con- trol register 0 (a-d conversion start bit) is set to 1 . when the ani (i = 11 through 0) comparator function select bit of the comparator function select register 0/1 = 0 and bit 3 of the a-d con- trol register 1 = 1 , a-d conversion ends 59 ad cycles after, and the interrupt request bit of the a-d conversion interrupt control register is set to 1 . at the same time, bit 6 of the a-d control register 0 (a-d conversion start bit) is cleared to 0 and this a-d conversion stops. the result of a-d conversion is stored into the a-d register corre- sponding to the selected pin. when the ani (i = 11 through 0) comparator function select bit of the comparator function select register 0/1 = 1 , a comparator operation ends 14 ad cycles after, and the interrupt request bit of the a-d con- version interrupt control register is set to 1 . at the same time, bit 6 of the a-d control register 0 (a-d conversion start bit) is cleared to 0 and the comparator operation stops. the result of the compari- son is stored into the bits of the comparator result register corre- sponding to the selected pin. fig. 78 bit configuration of a-d control register 0 a-d control register 0 address 1e 16 76543210 analog input select bits (note 1) (valid in the one-shot mode and repeat mode.) 0 0 0 : an 0 0 0 1 : an 1 0 1 0 : an 2 0 1 1 : an 3 1 0 0 : an 4 1 0 1 : an 5 1 1 0 : an 6 1 1 1 : an 7 (note 2) a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 or repeat sweep mode 1 fix this bit to 0 . a-d conversion start bit (note 3) 0 : a-d conversion stopped. 1 : a-d conversion started. a-d conversion frequency ( ad ) select bit 0 0 notes 1: invalid in the single sweep mode and repeat sweep mode 0. (each of these bits may be 0 or 1 .) 2: when using pin an 7 , make sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 3: use the movm (movmb) or sta (stab or stad) instruction for rewriting to this bit. 4: rewriting to each bit of the a-d control register 0 (except for bit 6) must be performed while a-d conversion is stopped.
70 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 79 bit configuration of a-d control register 1 fig. 80 bit configuration of a-d control register 2 notes 1: invalid in the one-shot mode and repeat mode. (each of these bits may be 0 or 1 .) 2: when using pin an 7 , make sure that the d-a 0 output enable bit (bit 0 at address 96 16 ) = 0 (output disabled). 3: once this bit is cleared from 1 to 0 , it is necessary to wait for 1 s or more before the a-d conversion starts. 4: rewriting to each bit of the a-d control register 1 must be performed while a-d conversion is stopped. 0 a-d sweep pin select bits (note 1) (valid in the single sweep mode and repeat sweep mode.) 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 an 3 (4 pins) 1 0 : an 0 an 4 (5 pins) 1 1 : an 0 an 7 (8 pins) (note 2) a-d operation mode select bit 1 0: modes other than repeat sweep mode 1 1: repeat sweep mode 1 resolution select bit 0: 8-bit resolution mode 1: 10-bit resolution mode a-d conversion frequency ( ad ) select bit 1 fix this bit to 0 . v ref connection select bit (note 3) 0 : v ref is connected. 1 : v ref is disconnected. 0 at read. 76543210 a-d control register 1 address 1f 16 a-d conversion frequency ( ad ) select bit bit 1 0 0 1 0 0 1 bit 0 ad f 2 /4 f 2 /2 f 2 1 1 f 1 (selectable only in 8-bit resolution mode) 76543210 analog input select bits (note 1) (valid in the one-shot mode and repeat mode) 0xxx : an 0 an 7 1000 : an 8 (note 2) 1001 : an 9 1010 : an 10 1011 : an 11 1100 : do not select. 1101 : do not select. 1110 : do not select. 1111 : do not select. 0 0 0 0 notes 1: invalid in the single sweep mode and repeat sweep mode 0 (each of these bits may be 0 or 1 .) 2: when using pin an 8 , make sure that the d-a 1 output enable bit (bit 1 at address 96 16 ) = 0 (output disabled). 3: rewriting to each bit of the a-d control register 2 must be performed while a-d conversion is stopped. a-d control register 2 address db 16
71 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers (2) repeat mode repeat mode is selected when bit 3 of the a-d control register 0 = 1 and bit 4 = 0 . the operation of this mode is the same as the operation of one-shot mode except that when a-d conversion for the selected pin is com- plete and the result is stored in the a-d register, conversion does not stop, but is repeated. no interrupt request is generated in this mode. furthermore, the a-d conversion start bit is not cleared. the contents of the a-d register can be read at any time. be sure not to write to the a-d register corresponding to the pins se- lected for a comparator during operation. (3) single sweep mode single sweep mode is selected when bit 3 of the a-d control register 0 = 0 and bit 4 = 1 . in the single sweep mode, the number of analog input pins to be swept can be selected. analog input pins are selected by bits 1 and 0 of the a-d control register 1 (address 1f 16 ). two pins, four pins, or five pins can be selected as analog input pins, depending on the contents of these bits. a-d conversion is performed only for selected input pins. after a-d conversion is performed for input of an 0 pin, the conversion result is stored in a-d register 0, and in the same way, a-d conversion is per- formed for selected pins one after another. after a-d conversion is performed for all selected pins, the sweep is stopped. a-d conversion is started when bit 6 of the a-d control register 0 (a-d conversion start bit) is set to 1 . when a-d conversion for all selected pins end, the interrupt request bit of the a-d conversion in- terrupt control register is set to 1 . at the same time, a-d conversion start bit is cleared to 0 and a-d conversion stops. (4) repeat sweep mode 0 repeat sweep mode 0 is selected when bit 3 of the a-d control reg- ister 0 = 1 and bit 4 = 1 . the difference from the single sweep mode is that a-d conversion does not stop after conversion for all selected pins, but repeats again from the an 0 pin. the repeat is performed among the selected pins. also, no interrupt request is generated. furthermore, the a-d convension start bit is not cleared. the contents of the a-d register can be read at any time. be sure not to write to the a-d register corresponding to the pins se- lected for a comparator during operation. (5) repeat sweep mode 1 repeat sweep mode 1 is selected when bit 3 of the a-d control reg- ister 0 = 1 and bit 4 = 1 , and bit 2 of the a-d control register 1 = 1 . the differences from the repeat sweap mode 0 are as follows: the a-d conversion for one unselected pin is performed each time when a-d conversion for selected pins is completed, and the a-d conversion is repeated once again from an 0 pin. the number of analog input pins to be swept. the analog input pins to be repeatedly swept are selected with bits 1 and 0 of the a-d control register 1. the contents of these pins are used to select one pin, two pins, three pins or four pins. the unselected pins are converted starting from the pin next to the pins selected as repeat sweep pins. no interrupt request is gener- ated. furthermore, the a-d conversion start bit is not cleared. the contents of the a-d register can be read at any time. be sure not to write to the a-d register, corresponding to the pins se- lected for a comparator, during operation. precaution for a-d conversion interrupts clear the interrupt request bit of the a-d conversion interrupt control register (bit 3 at address 70 16 ) before using an a-d conversion inter- rupt. it is because this interrupt request bit is undefined just after re- set.
72 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers d-a converter two independent d-a converters are included in this microcomputer, and each d-a converter adopts an 8-bit r-2r method. figure 81 shows the block diagram of the d-a converter, and figure 82 shows the bit configuration of the d-a control register (address 96 16 ). d-a conversion is performed by writing a value to the corresponding d-a register i. whether to output the analog voltage or not is deter- mined by bits 0 and 1 of the d-a control register. when any of bits 0 and 1 = ?? the corresponding pin (d-a 0 or d-a 1 ) outputs the analog voltage. this analog voltage (v) is determined according to value n. (??= decimal number. this has been set in the d-a register.) v = v ref ? n/256 (n = 0 to 255) v ref : reference voltage the contents of the corresponding d-a output enable bit and d-a register are cleared to ??at reset. an external buffer is necessary when connecting a low impedance load with the d-a converter. it is because that a d-a output pin does not include a buffer. pin d-ai (i = 0, 1) is multiplexed with i/o port pins, analog input pins, and external interrupt input pins. when a d-a i output enable bit = ? (in other words, output is enabled.), however, the corresponding pin cannot function as another i/o pin, which is multiplexed with pin d- ai. also, when not using the d-a converter, be sure to clear the contents of the corresponding d-a output enable bit and d-a register to ?? fig. 81 block diagram of d-a converter av ss v ref r-2r ladder resistor network d-a register i (i = 0, 1) (addresses 98 16 , 99 16 ) pin d-a i d-ai output enable bit data bus fig. 82 bit configuration of d-a control register d-a 0 output enable bit (note) 0: output is disabled. 1: output is enabled. d-a 1 output enable bit (note) 0: output is disabled. 1: output is enabled. 76543210 d-a control register address 96 16 note: pin d-ai is multiplexed with i/o port pins, analog input pins, and external interrupt input pins. when a d-ai output enable bit = ?? (in other words, output is enabled.), however, the corresponding pin cannot function as another i/o pin, which is multiplexed with pin d-ai.
73 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers 1/16 watchdog timer frequency select bit ?ff 16 ?is set. writing to watchdog timer register stp instruction watchdog timer interrupt request wf 32 wf 512 watchdog timer f 2 wait mode 1/16 1 0 ?watchdog timer register: address 60 16 ?watchdog timer frequency select register: bit 0 at address 61 16 ?watchdog timer clock source select bits at stp state termination: bits 6, 7 at address 61 16 ? when the most significant bit of the watchdog timer becomes ?? this signal will be generated. note: during the stop mode and until the stop mode is terminated, setting for disabling the watchdog timer is ignored. reset ? disables watchdog timer (note) . fx 16 fx 32 fx 64 fx 128 watchdog timer clock source select bits at stp state termination stop mode divided f(x in ) watchdog timer the watchdog timer is used to detect unexpected execution se- quence caused by software runaway and others. figure 83 shows the block diagram of the watchdog timer. the watchdog timer consists of a 12-bit binary counter. the watchdog timer counts clock wf 32 , which is obtained by dividing the peripheral devices clock f 2 by 16; or clock wf 512 , which is ob- tained by doing it by 256. bit 0 of the watchdog timer frequency se- lect register (watchdog timer frequency select bit) shown in figure 84 selects which clock is to be counted. wf 512 is selected when this bit 0 is 0 , and wf 32 is selected when bit 0 is 1 . bit 0 is cleared to 0 after reset. fff 16 is set in the watchdog timer when l level voltage is applied to pin reset, stp instruction is executed, data is written to the watchdog timer register (address 60 16 ), or the most significant bit of the watchdog timer becomes 0 . after fff 16 is set in the watchdog timer, when the watchdog timer counts wf 32 or wf 512 by 2048 counts, the most significant bit of the watchdog timer becomes 0 , the watchdog timer interrupt request bit is set to 1 , and fff 16 is set again in the watchdog timer. in program coding, make sure that data is written in the watchdog timer before the most significant bit of the watchdog timer becomes 0 . if this routine is not executed owing to unexpected program ex- ecution or others, the most significant bit of the watchdog timer be- fig. 83 block diagram of watchdog timer fig. 84 bit configuration of watchdog timer frequency select register 76543210 watchdog timer frequency select register watchdog timer frequency select bit 0 : w f 512 1 : w f 32 watchdog timer clock source select bits at stp state termination 0 0 : fx 32 0 1 : fx 16 1 0 : fx 128 1 1 : fx 64 76543210 address 61 16 comes 0 and an interrupt is generated. the microcomputer can generate a reset pulse by writing 1 to bit 6 (software reset bit) of processor mode register 0 in an interrupt rou- tine and can be restarted. the watchdog timer can also be used to return from the stp state, where a clock has stopped its operation owing to the stp instruction execution. for details, refer to the sections on the clock generating circuit and standby function. the watchdog timer stops its operation in the following cases, and at this time, input to the watchdog timer is disabled: when the external area is accessed in the hold state in the wait mode in the stop mode
74 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers how to disable watchdog timer when not using the watchdog timer, it can be disabled. when the watchdog timer is disabled, it s operation stops and no watchdog timer interrupt has been generated. setting for disabling the watchdog timer is possible by writing 79 16 and 50 16 to the particular function select register 2 (address 64 16 ) sequentially with the following instructions: movmb/stab instruction, or movm/sta instruction (m = 1) if any method other than above has been adopted in order to access (in other words, read/write) the particular function select register 2, the watchdog timer will not be disabled until reset operation is per- formed. (also, reset is the only one method to remove the setting for disabling the watchdog timer.) moreover, this setting for disabling the watchdog timer is ignored at return from the stp mode, and the watchdog timer operates. (for details, refer to the section on the standby function.)
75 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers input/output pins ports p1, p2, and p4 through p8 all have the direction register, and each bit can be programmed for input or output. a pin becomes an output pin when the corresponding bit of direction register is 1 , and an input pin when it is 0 . also, each bit of the port p6 direction register can be cleared to 0 by inputting a falling edge to pin p6out cut or by executing instruc- tions. each bit of the port p4 direction register can be cleared to 0 by inputting a falling edge to pin p4out cut or by executing instruc- tions. when a pin is programmed for output, the data is written to its port latch and it is output to the output pin. when a pin is programmed for output, the contents of the port latch is read instead of the value of the pin. accordingly, a previously output value can be read correctly even when the output h voltage is lowered or the output l voltage is raised owing to an external load, etc. a pin programmed as an input pin is in the flooting state, and the value input to the pin can be read. when a pin is programmed as an input pin, the data is written only in the port latch and the pin remains floating. each of figures 85 and 86 shows the block diagram for each port pin. when using a port pin as an internal peripheral device s input pin, clear the corresponding port direction register s bit to 0 . when us- ing a port pin as an internal peripheral device s output pin, the port direction register s bit may be 0 or 1 .
76 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 85 block diagram for each port pin (1) p1 3 /t x d 0 , p1 7 /t x d 1 p2 0 /ta4 out , p2 2 /ta9 out p6 0 /ta0 out /w/rtp0 0 , p6 1 /ta0 in /v/rtp0 1 , p6 2 /ta1 out /u/rtp0 2 , p6 3 /ta1 in /w/rtp0 3 , p6 4 /ta2 out /v/rtp1 0 , p6 5 /ta2 in /u/rtp1 1 , 1 p7 0 /an 0 , p7 1 /an 1 , p7 2 /an 2 , p7 3 /an 3 , p1 2 /r x d 0 , p1 6 /r x d 1 , p2 1 /ta4 in , p2 3 /ta9 in , p2 4 (/tb0 in ), p2 5 (/tb1 in ), p2 6 (/tb2 in ), p5 1 /int 1 , p5 5 /int 5 /tb0 in /idw, p5 6 /int 6 /tb1 in /idv, p5 7 /int 7 /tb2 in /idu 1 r p6out cut p2 7 p5 2 /int 2 /rtp trg1 , p5 3 /int 3 /rtp trg0 , p6 6 /ta3 out /rtp1 2 , p6 7 /ta3 in /rtp1 3 p7 4 /an 4 , p7 5 /an 5 , p7 6 /an 6 p8 2 /an 10 /rxd 0 p4 0 /ta5 out /rtp2 0 , p4 1 /ta5 in /rtp2 1 , p4 2 /ta6 out /rtp2 2 , p4 3 /ta6 in /rtp2 3 , p4 4 /ta7 out /rtp3 0 , p4 5 /ta7 in /rtp3 1 , 1 r p4out cut p4 6 /ta8 out /rtp3 2 , p4 7 /ta8 in /rtp3 3 , [inside dotted-line not included] [inside dotted-line included] [inside dotted-line not included] [inside dotted-line not included] [inside dotted-line included] [inside dotted-line included] data bus data bus data bus data bus data bus port latch port latch port latch port latch port latch direction register direction register direction register direction register direction register analog input output(internal peripheral devices) output(internal peripheral devices) output(internal peripheral devices) reset reset
77 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 86 block diagram for each port pin (2) p7 7 /an 7 /da 0 p1 0 /cts 0 /rts 0 p1 1 /cts 0 /clk 0 p1 4 /cts 1 /rts 1 p1 5 /cts 1 /clk 1 1 0 p8 1 /an 9 /cts 2 /clk 2 p8 0 /an 8 /cts 2 /rts 2 /da 1 p8 3 /an 11 /t x d 2 1 p4out cut /int 0 , p6out cut /int 4 1 0 analog input analog output enable d-a output analog input analog input analog output enable d-a output [inside dotted-line not included] [inside dotted-line included] analog input data bus data bus port latch direction register port latch direction register data bus data bus port latch direction register port latch direction register output (internal peripheral devices) output (internal peripheral devices) output (internal peripheral devices)
78 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 88 microcomputer internal register? status at reset (2) reset circuit while the power source voltage satisfies the recommended operat- ing condition, reset state is removed if pin resets level returns from the stabilized ??level to the ??level. as a result, program ex- ecution starts from the reset vector address. this reset vector ad- dress is expressed as shown below: ?a 23 to a 16 = 00 16 ?a 15 to a 8 = contents at address ffff 16 ?a 7 to a 0 = contents at address fffe 16 figures 87 and 88 show the microcomputer internal registers status at reset, and figure 89 shows an operation example of the reset cir- cuit. apply ??level voltage to pin reset for a period (10 ? or more) under the following conditions: ?pin vccs level satisfies the recommended operating condition. ?oscillators operation has been stabilized. fig. 89 operation example of reset circuit (note that proper evalua- tion is necessary in the system development stage.) ( db 16 ) ( a6 16 ) ( a8 16 ) ( a9 16 ) ( aa 16 ) ( d7 16 ) ( ac 16 ) ( ae 16 ) ( c4 16 ) ( d6 16 ) ( d8 16 ) ( d9 16 ) ( da 16 ) 00 0 00 16 00 16 0000 16 fff 16 1?? 0 00 ? ? 0 0 0 0000 0000 0000 0000 0000 ( f5 16 ) ( f6 16 ) ( f7 16 ) 0 00 000 ( f9 16 ) 000 ( fe 16 ) 0 00 000 ( fd 16 ) ( f8 16 ) ( ff 16 ) 0 00 00 16 00 16 00 16 00 16 00 16 00 16 000 0 000 0 00 16 00 16 00 16 ( a0 16 ) ( a2 16 ) ( a4 16 ) 00 16 00 16 00 16 0 0 1 0 0000 ( b4 16 ) 0 000 0010 ( b5 16 ) ( b0 16 ) 00 16 0 0 0 001 0111 ( bc 16 ) 00 0 ( dd 16 ) ( de 16 ) 00 16 00 16 ( dc 16 ) 00 16 ( df 16 ) 00 16 0000 0000 ( f1 16 ) ( f2 16 ) waveform output mode register three-phase output data register 0 three-phase output data register 1 pulse output control register pulse output data register 0 pulse output data register 1 uart2 transmit/receive mode register uart2 transmit/receive control register 0 uart2 transmit/receive control register 1 uart2 transmit interrupt control register uart2 receuve interrupt control register position-data-retain function control register serial i/o pin control register port p2 pin function control register note: the contents of the other registers and ram are undefined at reset and must be initialized by software. timer a6 mode register clock control register 0 a-d control register 2 up-down register 1 timer a5 mode register timer a7 mode register timer a8 mode register timer a9 mode register address address contents at address ffff 16 contents at address fffe 16 program bank register pg program counter pc h program counter pc l direct page registers dpr0 to dpr3 data bank register dt stack pointer processor status register ps int 7 interrupt control register timer a5 interrupt control register timer a6 interrupt control register timer a7 interrupt control register timer a9 interrupt control register int 6 interrupt control register int 5 interrupt control register timer a8 interrupt control register comparator function select register 0 comparator function select register 1 comparator result register 0 comparator result register 1 v cc reset power on v cc level 0.2v cc level oscillation stabilized 10 s x in 0v 0v 0v
79 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 87 microcomputer internal register? status at reset (1) 0 0 00 00 00 0 0 0 ( 05 16 ) ( 08 16 ) 00 16 ( 0d 16 ) ( 10 16 ) ( 11 16 ) ( 56 16 ) 00 16 ( 57 16 ) 00 16 ( 58 16 ) 00 16 ( 59 16 ) 00 16 ( 5a 16 ) 00 16 0 000 0 ( 1e 16 ) 0 000 0?? ( 1f 16 ) 1 0 0 000 ( 34 16 ) 1 0 0 000 ( 3c 16 ) 0 000 0 010 ( 35 16 ) 0 000 0 010 ( 3d 16 ) 0 0 000 ( 42 16 ) 00 ( 45 16 ) ( 30 16 ) 00 16 ( 38 16 ) 00 16 0 ( 44 16 ) ( 40 16 ) 00 16 0 0? 0 000 ( 5b 16 ) 1 000 0 0 ( 5e 16 ) ( 5f 16 ) ( 60 16 ) 0 1 0000 0000 0 fff 16 ( 61 16 ) ( 62 16 ) ( 63 16 ) ( 66 16 ) ( 67 16 ) ( 6e 16 ) ( 6f 16 ) 0000 ?000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ( 72 16 ) ( 73 16 ) ( 74 16 ) ( 77 16 ) ( 78 16 ) ( 79 16 ) ( 7a 16 ) 00 ( 7c 16 ) ( 98 16 ) ( 70 16 ) ( 71 16 ) ( 75 16 ) ( 76 16 ) ( 96 16 ) ( 7b 16 ) ( 99 16 ) 00 16 00 00 00 16 0 0 ?? ? 0000 0 0000 0 0 00 0 0 ( 43 16 ) 0 0 000 0 ( 41 16 ) 0000 0 0 0 0 000 0 1 0 0 00 16 00 16 0 0? 0 000 ( 5c 16 ) 0 0 0? 0 000 ( 5d 16 ) 0 ( 0c 16 ) 00 16 00 0 ( 14 16 ) 000 0 0 00 00 0 000 ( 7e 16 ) 0 00 000 ( 7d 16 ) ( 7f 16 ) 0 00 address port p1 direction register port p2 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register timer a0 mode register timer a1 mode register timer a2 mode register timer a3 mode register timer a4 mode register notes 1: the contents of the other registers and ram are undefined at reset and must be initialized by software. 2: at power-on reset, these bits are clear to 0 . at hardware or software reset, on the other hand, these bits retain the value just before reset. a-d control register 0 a-d control register 1 uart 0 transmit/receive control register 0 uart 1 transmit/receive control register 0 uart 0 transmit/receive control register 1 uart 1 transmit/receive control register 1 one-shot start register 0 timer a clock frequency select register uart 0 transmit/receive mode register uart 1 transmit/receive mode register up-down register 0 count start register 0 timer b0 mode register processor mode register 0 processor mode register 1 address watchdog timer watchdog timer frequency select register particular function select register 0 particular function select register 1 debug control register 0 debug control register 1 d-a register 1 int 3 interrupt control register int 4 interrupt control register uart 0 receive interrupt control register uart 1 transmit interrupt control register uart 1 receive interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b2 interrupt control register d-a register 0 a-d conversion interrupt control register uart 0 transmit interrupt control register timer a0 interrupt control register timer a1 interrupt control register d-a control register timer b1 interrupt control register int 0 interrupt control register int 1 interrupt control register int 2 interrupt control register (note 2) (note 2) (note 2) one-shot start register 1 count start register 1 timer b1 mode register timer b2 mode register
80 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers oscillation circuit an oscillation circuit locates between pins x in and x out , and figure 90 shows a circuit example with an external ceramic resonator or quartz crystal oscillator. the constants such as capacitance etc. de- pend on a resonator/oscillator. therefore, for these constants, adopt the resonator/oscillator manufacturers recommended values. figure 91 shows a circuit example with an external clock source. when an external clock is input, be sure to leave pin x out open. also, in this case, when the external clock input select bit (bit 1 of the particular function select register 0; see figure 95.) is set to ?? the oscillation circuit stops its operation and resumes the current dissi- pation. moreover, this bit has another function, which selects the re- turn condition from the stop mode. for details, refer to the section on the standby function. on the other hand, the pll (phase locked loop) frequency multi- plier (hereafter, referred to as pll circuit.) is included, also. this pll circuit uses a clock input from pin x in and generates a multiplicated clock. when using the pll circuit, be sure to connect pin v cont with an external filter circuit. (see figure 92.) when not using the pll cir- cuit, be sure to leave pin v cont open. when not using the pll circuit, be sure to clear the pll circuit op- eration enable bit (bit 1 of the clock control register 0; see figure 94.), so that the pll circuit will stop its operation. fig. 90 circuit example with external ceramic resonator or quartz-crystal oscillator fig. 91 circuit example with external clock source fig. 92 circuit example of connection with pin v cont when pll cir- cuit used x in r f x out r d c in c out m37905 m37905 x in x out left open. external clock source vcc vss m37905 v cont 1 k ? note: make the wiring length as short as possible, and shield it with the gnd line which surrounds this circuit. also, for the clock supply to pin x in , see figures 90 and 91.
81 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers clock generating circuit figure 93 shows the block diagram of the clock generating circuit. the clock generating circuit consists of the clock oscillation circuit, pll frequency multiplier (pll circuit), system clock switch circuit, pe- ripheral devices clock switch circuit, clock divider, standby control circuit, etc. as control registers for the clock generating circuit, also, the clock control register 0 (address bc 16 ), particular function select register 0 (address 62 16 ) are provided. (see figures 94 and 95.) as shown in figure 93, clocks used in the cpu, biu, peripheral de- vices, watchdog timer (in other words, clocks cpu , biu , f 1 to f 4096 , wf 32 , wf 512 ) are made from system clock f sys . system clock f sys can be selected between fx in (in other words, a clock input from pin x in) and f pll (in other words, an output clock generated by the pll cir- cuit. the pll circuits operation, system clock (f sys ) selection, and divi- sion ratio selection for peripheral devices?clocks (f 1 to f 4096 ) are con- trolled by the clock control register. the following describes about these control. bit 1 of the clock control register 0 (the pll circuit operation enable bit) selects the pll circuits operation (inactive/active). when this bit is set to ?? pin v cont will becomes valid, and the pll circuit will be active. at reset, the pll circuit operation enable bit becomes ?? (in this case, the pll circuit is active.) when not using the pll circuit, be sure to clear the pll circuit operation enable bit to ??(inactive). at the stp instruction execution, the pll circuit is inactive, and pin v cont is invalid, regardless of this bit 1s status. bits 2 and 3 of the clock control register (the pll multiplication ratio select bits) select the ratio of f pll /fx in . the pll multiplication ratio must be set so that the frequency of f pll must be in the range from 10 mhz to 20 mhz. at reset, the pll multiplication ratio select bits become ?,1?( ? 2). the change of the pll multiplication ratio must be performed while input clock fx in is selected as the system clock. (in this case, bit 5 of the clock control register 0 = ??) after that, be sure to wait that the operation-stabilizing time of the pll circuit has passed, and switch the system clock to f pll . (in other words, set bit 5 to ??) note that, after reset, the pll multiplication ratio select bits are allowed to be changed only once. bit 5 of the clock control register 0 is the system clock select bit, and input clock fx in is selected as the system clock when bit 5 = ?? on the other hand, when bit 5 = ?? f pll is selected. at reset, the system clock select bit becomes ?? when selecting f pll , be sure that the pll circuits operation has fully been stabilized, and then, set the system clock select bit to ?? also, when the pll circuit operation enable bit is cleared to ??(the pll circuit is inactive . ), the system clock select bit will automatically be cleared to ?? note that a value of ??cannot be written to the system clock select bit while the pll circuit operation enable bit =?? table 9 lists the f sys selection. bits 6 and 7 of the clock control register 0 are the peripheral devices clock select bits 0, 1, and these bits select the division ratio of (f 1 to f 4096 )/(f sys ). table 10 lists the internal peripheral devices operation clock fre- quency. at reset, these bits become ?, 0? table 9. f sys selection table 10. internal peripheral devices?operation clock frequency 10 ( ? 3) 01 ( ? 2) system clock f sys 11 ( ? 4) fx in f pll f pll f pll clock source frequency (note) note: the pll multiplication ratio must be set so that the frequency of f pll must be in the range from 10 mhz to 20 mhz. f(x in ) means the frequency of the input clock from pin x in (fx in ). after reset, the pll multiplication ratio select bits are allowed to be changed only once. pll circuit operation enable bit (bit 1) system clock select bit (bit 5) 1 0 1 f(x in ) f(x in ) ? 2 f(x in ) ? 3 f(x in ) ? 4 pll multiplication ratio select bits (bits 3, 2) (note) f sys /16 f sys /2 peripheral devices? clock select bits 1, 0 (bits 7, 6) f sys /64 f sys f sys f sys /8 f sys /32 1 0 1 1 note: when selecting the peripheral devices? clock select bits 1, 0 = 01 2 , be sure that system clock f sys does not exceed 10 mhz. internal peripheral devices? operation clock f 1 f 16 f sys /2 f sys /4 f sys /32 f sys /128 0 1 (note) 0 0 f 2 f 64 f 512 f 4096 f sys f sys /512 f sys /4096 f sys /256 f sys /2048 f sys /1024 f sys /8192 do not select.
82 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 93 block diagram of clock generating circuit f 2 f 64 f 512 f 4096 q r s stp instruction biu (clock for biu) cpu (clock for cpu) cpu wait request 1/4 1/8 1/8 reset watchdog timer frequency select bit : bit 0 at address 61 16 watchdog timer clock source select bits at stop state termination : bits 6, 7 at address 61 16 external clock input select bit : bit 1 at address 62 16 system clock stop select bit at wit : bit 3 at address 63 16 pll circuit operation enable bit : bit 1 at address bc 16 pll multiplication ratio select bits : bits 2, 3 at address bc 16 system clock select bit : bit 5 at address bc 16 peripheral device s clock select bits 0, 1 : bits 6, 7 at address bc 16 1/8 1/2 1/16 watchdog timer wf 32 wf 512 f 16 f 1 peripheral device s clocks 0 1 watchdog timer frequency select bit x in x out system clock stop select bit at wit 1/16 0 1 watchdog timer clock source select bit at stop state termination wait mode 1 0 1 0 1/2 1 0 1 wait mode system clock select bit pll frequency multiplier f pll v cont wait mode external clock input select bit q r s stp instruction interrupt request q r s wit instruction interrupt request wait mode pll circuit operation enable bit pll multiplication ratio select bits fx in f/n 0 fx 16 fx 32 fx 64 fx 128 fx 16 fx 32 fx 64 fx 128 peripheral device s clock select bit 0 peripheral device s clock select bit 1 biu : bus interface unit cpu : central processing unit ? : signal generated when the watchdog timer s most significant bit becomes 0 f sys system clock frequency select bit ? operating clock for serial i/o, timer b a-d conversion frequency ( ad ) clock source operating clock for timer a external clock input select bit interrupt request
83 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 95 bit configuration of particular function select register 0 fig. 94 bit configuration of clock control register 0 76543210 particular function select register 0 external clock input select bit (note) 0: oscillation circuit is active. (the oscillator is connected.) watchdog timer is used at stop mode termination. 1: oscillation circuit is inactive. (the externally-generated clock is input.) when the system clock select bit = 0 , watchdog timer is not used at stop mode termination. when the system clock select bit = 1 , watchdog timer is used at stop mode termination. fix this bit to 0 . stp instruction invalidity select bit (note) 0: stp instruction is valid. 1: stp instruction is invalid. note: address 62 16 00 0 writing to these bits requires the following procedure: write 55 16 to this register. (the bit status does not change only by this writing.) succeedingly, write 0 or 1 to each bit. also, use the movm (movmb) instruction or sta (stab, stad) instruction 76543210 clock control register 0 fix this bit to 1 . pll circuit operation enable bit (note 1) 0: pll frequency multiplier is inactive, and pin v cont is invalid (floating state). 1: pll frequency multiplier is active, and pin v cont is valid. pll multiplication ratio select bits (note 2) 00: do not select. 01: double 10: triple 11: quadruple fix this bit to 1 . system clock select bit (note 3) 0: fx in 1: f pll peripheral device s clock select bits 1, 0 see table 10. address bc 16 1 1 notes 1: when not using the pll frequency multiplier, be sure to clear this bit to 0 . in the stop mode, the pll circuit is inactive regardless of this bit s content; at this time, pin v cont is invalid. 2: when rewriting this bit, be sure to clear bit 5 to 0 simultaneously. also, after this bit is rewritten, insert a waiting time of 2 ms, and then set bit 5 to 1 . 3: when the pll circuit operation enable bit (bit 1) has been cleared to 0 , this bit will also be cleared to 0 . when bit 1 = 0 , nothing can be written to this bit. (fixed to be 0 .)
84 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers standby function the standby function provides the stop (hereafter called stp) and the wait (hereafter called wit) mode. these modes are used to save the power dissipation of the system, by making oscillation or system clock inactive in the case that the cpu needs not be active. the microcomputer enters the stp or wit mode by executing the stp or wit instruction, and either mode is terminated by acceptance of an interrupt request or reset. to terminate the stp or wit mode by an interrupt request, the inter- rupt to be used for termination of the stp or wit mode must be en- abled in advance to execution of the stp or wit instruction. the interrupt priority level of this interrupt needs to be higher than the processor interrupt priority level (ipl) of the routine where the stp or wit instruction will be executed. figures 95 shows the bit configuration of the particular function se- lect register 0, figure 96 shows the bit configuration of the particular function select register 1, and figure 97 shows the bit configuration of the watchdog timer frequency select register. setting the stp in- struction invalidity select bit (bit 0 of the particular function select reg- ister 0) to 1 invalidates the stp instruction, and the stp instruction will be ignored. since the above bit is cleared to 0 after reset is re- moved, however, the stp instruction is valid. the stp- or the wit-instruction-execution status bit (bit 0 or 1 of the particular function select register 1) is set to 1 by the execution of the stp or the wit instruction, and so, after the stp or wit mode has been terminated, each bit will indicate that the stp or wit in- struction has been executed. accordingly, each of these bits must be cleared to 0 by software at termination of the stp or the wit mode. table 11 explains the microcomputer s operation in the stp and wit modes. stp mode the execution of the stp instruction makes the oscillation circuit and pll circuit inactive. it also makes the following inactive: input clock fx in , system clock f sys , biu , cpu , and peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 with the l state, and divide clocks fx 16 to fx 128 with the h state. in the watchdog timer, fff 16 is automati- cally set. as shown in figure 93, any one of divide clocks fx 16 to fx 128 , which is selected by the watchdog timer clock source select bits at stp termination (bits 6 and 7 of the watchdog timer frequency select register), becomes the watchdog timer s clock source. in the stp mode, the a-d converter and watchdog timer, which uses peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 , are inactive. at this time, timers a and b can be active only in the event counter mode, and serial i/o communication is active while an external clock is selected. the stp mode is terminated by acceptance of an interrupt request or reset, and the oscillation circuit and pll circuit restart their opera- tions. input clock fx in , system clock f sys , and peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 are also supplied. when the stp mode is terminated by reset, supply of biu and cpu starts immediately after the oscillation circuit and pll circuit restart their operations. therefore, the reset input must be raised h after the operation-stabilizing time for these circuits has passed. the following two modes are available in order to terminate the stp mode by an interrupt: (1) the watchdog timer is used in order to measure the period from the operation restart of the oscillation circuit and pll circuit until the supply start of biu and cpu. (2) the supply of biu and cpu is started immediately after the op- eration restart of the oscillation circuit and pll circuit. mode wit system clock stop select bit at wit active (note 1) oscillation circuit operations of function while wit, stp modes 0 f sys , (note 1) 1 inactive ( l ) inactive ( l ) inactive ( l ) inactive timers a, b: operation is enabled only in the event counter mode. serial i/o: operation is enabled only while an external clock is selected. a-d converter: inactive . (watchdog timer: inactive ) pll circuit active (note 2) active (note 2) inactive notes 1: when the external clock input select bit = 1 , the oscillation circuit is inactive. also, clock input from pin x in is allowed. 2: when the pll circuit operation enable bit = 0 , the pll circuit is inactive. ? table 11. microcomputer s operation in stp and wit modes
85 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 96 bit configuration of particular function select register 1 fig. 97 bit configuration of watchdog timer frequency select register 76543210 watchdog timer frequency select register watchdog timer frequency select bit 0 : select w f 512 1 : select w f 32 watchdog timer clock source select bits at stp termination 0 0 : fx 32 0 1 : fx 16 1 0 : fx 128 1 1 : fx 64 76543210 address 61 16 when the external clock input select bit (bit 1 of the particular func- tion select register 0) = 0 or the system clock select bit (bit 5 of the clock control register 0) = 1 , the watchdog timer will start counting down with one of the above divide clocks, fx 16 to fx 128 , after the os- cillation circuit and pll circuit have been restarted their operations owing to an interrupt. the most significant bit of the watchdog timer reaching 0 , supply of biu and cpu restarts. on the other hand, when the external clock input select bit = 1 and the system clock select bit = 0 , supply of biu and cpu will restart immediately after the oscillation circuit and pll circuit have been re- started their operations owing to an interrupt. (in actual fact, after the selected one of the above divide clocks, fx 16 to fx 128 , has been changed from h to l , this supply will restart.) 76543210 particular function select register 1 stp-instruction-execution status bit (note 1) 0: normal operation. 1: stp instruction is under execution. wit-instruction-execution status bit (note 1) 0: normal operation. 1: wit instruction is under execution. fix this bit to 0 . system clock stop select bit at wit (note 2) 0: in wait mode, system clock f sys is active. 1: in wait mode, system clock f sys is inactive. fix this bit to 0 . timer b2 clock source select bit valid in event counter mode: 0: clock input from pin tb2 in is counted. 1: fx 32 (f(x in )/32) is counted. address 63 16 notes 1: at power-on reset, this bit becomes 0 . at hardware reset or software reset, this bit retains the value just before reset. even when 1 is try to be written, the bit status will not change. 2: setting this bit to 1 must be performed just before execution of the wit instruction. also, after the wait state is terminated, this bit must be cleared to 0 immediately. 42 00
86 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers wit mode when the wit instruction is executed with the system clock stop se- lect bit at wit (bit 3 of the particular function select register 1 in fig- ure 93) being 0 , biu , cpu , and divide clocks wf 32 and wf 512 are inactive with the l state. however, the oscillation circuit, pll circuit, input clock fx in , system clock f sys , 1 , and peripheral devices clocks f 1 to f 4096 remain active. therefore, biu and cpu are inactive, where as timers a and b, serial i/o, and the a-d converter, which use the peripheral devices clocks f 1 to f 4096 , are still active. note that the watchdog timer is inactive. on the other hand, when the wit instruction is executed with the system clock stop select bit at wit being 1 , the oscillation circuit, pll circuit, and input clock fx in are active, while system clock f sys , biu , cpu , and peripheral devices clocks are inactive. as a result, the a-d converter and watchdog timer, which use peripheral devices clocks f 1 to f 4096 , wf 32 and wf 512 , become inactive. at this time, tim- ers a and b are active only in the event counter mode, and serial i/o communication is active only while an external clock is selected. if the internal peripheral devices are not used in the wit mode, the lat- ter is better because the current dissipation is more saved. note that the system clock stop select bit at wit needs to be set to 1 immedi- ately before execution of the wit instruction and cleared to 0 im- mediately after the wit mode is terminated. the wit state is terminated by acceptance of an interrupt request, and then, supply of biu and cpu will restart. since the oscillation circuit, pll circuit, and clock input fx in are active in the wit mode, an interrupt processing can be executed just after the wit mode ter- mination.
87 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers power saving function the following functions can save the power dissipation of the whole system. (1) inactive system clock in wait mode in the wait mode, if the internal peripheral devices need not to oper- ate, when the system clock stop select bit at wit (bit 3 of the particu- lar function select register 1) = 1 , both of system clock f sys and peripheral devices clock are inactive, and the power dissipation can be saved. for details, refer to the section on the standby function. (2) inactive oscillation circuit when an externally-generated stable clock is input to pin x in , the power dissipation can be saved if both of the following conditions are met: the external clock input select bit (bit 1 of the particular function select register 0) = 1 . the oscillation driver circuit between pins x in and x out is inactive. at this time, the output level at pin x out is fixed to h . when not using f pll , also, the supply of (3) disconnection from pin v ref when not using the a-d converter, by setting the v ref connection select bit (bit 6 of the a-d control register 1) to 1 , the resistor ladder network of the a-d converter will be disconnected from the reference voltage input pin (v ref ). in this case, no current flows from pin v ref to the resistor ladder network, and the power dissipation can be saved. note that, after the v ref connection select bit changes from 1 (v ref disconnected) to 0 (v ref connected), be sure that a wait- ing time of 1 ? or more has passed before the a-d conversion starts. for details, refer to the section on the a-d converter.
88 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 98 block diagram of debug function address compare register 0 address compare register 1 debug control register 0 matching compare register matching compare register address matching detect circuit debug control register 1 internal data bus (db 0 to db 15 ) cpu bus (address) address matching detection interrupt debug function when the cpu fetches an instruction code, an interrupt request will be generated if a selected condition is satisfied, as a resultant of comparison between a specified address and the start address where the instruction code is stored (the contents of pg and pc). the decision whether this condition is satisfied or not is called ad- dress matching detection, and the interrupt generated by this detec- tion is called an address matching detection interrupt. (for interrupt vector addresses, refer to the section on interrupts.) in the address matching detection, a non-maskable interrupt routine is proceeded without execution of the original instruction which has been allocated to the target address. the debug function provides the following two modes: the address matching detection mode, which is used to avoid the area where program exists or modify a program. the out-of-address-area detection mode, which is used to detect a program runaway. figure 98 shows the block diagram of the debug function. figures 99 and 100 show the bit configurations of the debug control registers 0, 1, and address compare registers 0,1, respectively. the detect condition select bits of the debug control register 0 can select one condition between the following 4 conditions. when the selected address condition is satisfied, an address matching detec- tion interrupt request will be generated: (1) address matching detection 0 the contents of pg and pc match with the address which has been set in the address compare register 0. (2) address matching detection 1 the contents of pg and pc match with the address which has been set in the address compare register 1. (3) address matching detection 2 the contents of pg and pc match with the address which has been set in either of the address compare register 0 or address compare register 1. (4) out-of-address-area detection the contents of pg and pc are less than the address which has been set in the address compare register 0 or larger than the ad- dress which has been set in the address compare register 1. by setting the detect enable bit of the debug control register 0 to 1 , an address matching detection interrupt request will be generated if any one of the above address conditions is satisfied. clearing the detect enable bit to 0 generates no interrupt request even if any of the above address conditions is satisfied. the address compare register access enable bit of the debug con- trol register 1 must be set to 1 by the instruction just before the ac- cess operation (read/write). then, this bit must be cleared to 0 (disabled) by the next instruction. while this bit = 0 , the address compare registers 0, 1 cannot be accessed. the address-matching-detection 2 decision bit of the debug control register 1 decides, whether the address which has been set in the address compare register 0 or 1 matches with the contents of pg, pc, when the address matching detection 2 is selected. the con- tents of this bit is invalid when address matching detection 0 or 1 is selected. in order to use the debug function to avoid the area where program exists or modify a program, perform the necessary processing within an address matching interrupt routine. as a result, the contents of pg, pc, ps at acceptance of an address matching detection inter- rupt request (i.e. the address at which an address matching detec- tion condition is satisfied) have been pushed onto the stack. if a return destination address after the interrupt processing is to be al- tered, rewrite the contents of the stack, and then return by the rti instruction. to use the debug function to detect a program runaway, set an ad- dress area where no program exists into the address compare regis- ters 0 and 1 by using the out-of-address-area detection. when the cpu fetches instruction codes from this address area and executes them, an address matching detection interrupt request will be gener- ated. the above debug function cannot be evaluated by a debugger, so that the debug function must not be used while a debugger is run- ning.
89 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers fig. 99 bit configuration of debug control register 0, 1 fig. 100 bit configuration of address compare register 0, 1 76543210 debug control register 0 detect condition select bits (note 1) 000: do not select. 001: address matching detection 0 010: address matching detection 1 011: address matching detection 2 100: do not select. 101: out-of-address-area detection 110: do not select. 111: do not select. fix this bit to 0 (note 1) . detect enable bit (note 1) 0: detection disabled. 1: detection enabled. fix this bit to 0 (note 1) . 1 at read. address 66 16 76543210 debug control register 1 fix this bit to 0 (note 1) . 0 at read (note 1) . address compare register access enable bit (note 2) 0: disabled 1: enabled fix this bit to 1 when using the debug function. while debugger is not used, 0 at read. while debugger is used, 1 at read. address-matching-detection 2 decision bit ? 0 at read. address 67 16 0 0 0 0 1 1 0 notes 1: at power-on reset, these bits = 0 ; at hardware reset or software reset, these bits retain the value just before reset. 2: set this bit to 1 with the instruction just before the address compare register 0, 1 (addresses 68 16 to 6d 16 ) is accessed. and then, clear this bit to 0 with the instruction just after the access. 0 address compare register 0 address compare register 1 the address to be detected (in other words, the start address of instruction) is set here. address 68 16 , 69 16 , 6a 16 6b 16 , 6c 16 , 6d 16 (23) 7 (8) (15) (16) 0 7 0 7
90 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers unit v v v v v v ma ma ma ma ma ma mhz mhz max. 5.5 vcc 0.2 v cc ?0 ? 10 20 5 15 20 20 parameter power source voltage analog power source voltage power source voltage analog power source voltage high-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3 , p4out cut , p6out cut , x in , reset, md0, md1 low-level input voltage p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3 , p4out cut , p6out cut , x in , reset, md0, md1 high-level peak output current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 high-level average output current p1 0 ?1 7 , p2 0 ?2 7 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 low-level peak output current p1 0 ?1 7 , p2 0 ?2 7 , p5 1 ?5 3 , p5 5 ?5 7 , p7 0 ?7 7 low-level peak output current p4 0 ?4 7 , p6 0 ?6 7 low-level average output current p1 0 ?1 7 , p2 0 ?2 7 , p5 1 ?5 3 , p5 5 ?5 7 , p7 0 ?7 7 low-level average output current p4 0 ?4 7 , p6 0 ?6 7 external clock input frequency (note 1) system clock frequency symbol v cc av cc v ss av ss v ih v il i oh(peak) i oh(avg ) i ol(peak) i ol(peak) i ol(avg) i ol(avg) f(x in ) f(f sys ) parameter power source voltage analog power source voltage input voltage p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3 , p4out cut , p6out cut , v cont , v ref , x in , reset, md0, md1 output voltage p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3, x out power dissipation operating ambient temperature storage temperature symbol v cc av cc v i v o p d t opr t stg absolute maximum ratings recommended operating conditions (vcc = 5 v, ta = ?0 to 85 ?, unless otherwise noted) notes 1: when using the pll frequency multiplier, be sure that f(f sys ) = 20 mhz or less. 2: the average output current is the average value of an interval of 100 ms. 3: the sum of i ol(peak) must be 110 ma or less, the sum of i oh(peak) must be 80 ma or less. unit v v v v mw ? ? ratings ?.3 to 6.5 ?.3 to 6.5 ?.3 to v cc +0.3 ?.3 to v cc +0.3 300 ?0 to 85 ?0 to 150 limits min. 4.5 0.8 vcc 0 typ. 5.0 v cc 0 0
91 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers unit v v v v v a a v ma a f(f sys ) = 20 mhz. cpu is active. ta = 25 c when clock is inactive. ta = 85 c when clock is inactive. test conditions i oh = ?0 ma i ol = 10 ma v i = 5.0 v v i = 0 v when clock is inactive. parameter high-level output voltage p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3 low-level output voltage p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3 hysteresis ta0 in ?a9 in , ta0 out ?a9 out , tb0 in ?b2 in , int 0 ?nt 7 , cts 0 , cts 1 , cts 2 , clk 0 , clk 1 , clk 2 , rxd 0 , rxd 1 , rxd 2 , rtp trg0 , rtp trg1 , p4out cut , p6out cut hysteresis reset hysteresis x in high-level input current p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3 , p4out cut , p6out cut , x in , reset, md0, md1 low-level input current p1 0 ?1 7 , p2 0 ?2 7 , p4 0 ?4 7 , p5 1 ?5 3 , p5 5 ?5 7 , p6 0 ?6 7 , p7 0 ?7 7 , p8 0 ?8 3 , p4out cut , p6out cut , x in , reset, md0, md1 ram hold voltage power source current symbol v oh v ol v t+ vt v t+ vt v t+ vt i ih i il v ram i cc dc electrical characteristics (vcc = 5 v, vss = 0 v, ta = ?0 to 85 ?, f(f sys ) = 20 mhz, unless otherwise noted) min. 3 0.4 0.5 0.1 2 limits typ. 25 max. 2 1 1.5 0.3 5 ? 50 1 20 output-only pins are open, and the other pins are con- nected to vss or vcc. an external square-waveform clock is input. (pin x out is open.) the pll frequency multiplier is inac- tive.
92 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers resolution absolute accuracy ladder resistance conversion time reference voltage analog input voltage r ladder t conv v ref v ia v ref = v cc v ref = v cc v ref = v cc f(f sys ) 20 mhz max. a-d converter characteristics (v cc = av cc = 5 v ?0.5 v, v ss = av ss = 0 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol test conditions limits min. 10-bit resolution mode 8-bit resolution mode comparater 10-bit resolution mode 8-bit resolution mode comparater 5 5.9 2.45 (note) 0.7 (note) 2.7 0 10 ?3 ?2 ?40 v cc v ref bits v lsb lsb mv k ? s v v note: this is applied when a-d conversion freguency ( ad ) = f 1 ( ). d-a converter characteristics (v cc = 5 v, v ss = av ss = 0 v, v ref = 5 v, t a = ?0 to 85 ?, unless otherwise noted) unit parameter symbol limits typ. min. max. test conditions resolution absolute accuracy set time output resistance reference power source input current t su r o i vref (note) 2 3.5 8 ?1.0 3 4.5 3.2 bits % s k ? ma note: the test conditions are as follows: ?one d-a converter is used. ?the d-a register value of the unused d-a converter is ?0 16 . ?the reference power source input current for the ladder resistance of the a-d converter is excluded. s reset input low-level pulse width t w(resetl) symbol parameter min. limits unit reset input reset input timing requirements (v cc = 5 v ?0.5 v, v ss = 0v, ta = ?0 to 85 ?, unless otherwise noted) 10 max. typ. reset input t w(resetl) a-d converter comparator 256 1 v ref typ.
93 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c(ta) t w(tah) t w(tal) f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz peripheral device input/output timing (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(f sys ) = 20 mhz unless otherwise noted) ? for limits depending on f(f sys ), their calculation formulas are shown below. also, the values at f(f sys ) = 20 mhz are shown in ( ). timer a input (up-down input and count input in event counter mode) t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in -up) symbol tai out input cycle time tai out input high-level pulse width tai out input low-level pulse width tai out input setup time tai out input hold time parameter limits min. 2000 1000 1000 400 400 max. ns ns ns ns ns unit timer a input (external trigger input in pulse width modulation mode) t w(tah) t w(tal) symbol tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 80 limits max. ns ns unit limits symbol parameter min. max. unit 8 10 9 f(f sys ) (400) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns 80 80 timer a input (external trigger input in one-shot pulse mode) limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(ta) t w(tah) t w(tal) tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width ns ns ns timer a input (gating input in timer mode) note : the tai in input cycle time requires 4 or more cycles of a count source. the tai in input high-level pulse width and the tai in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. timer a input (count input in event counter mode) t c(ta) t w(tah) t w(tal) symbol tai in input cycle time tai in input high-level pulse width tai in input low-level pulse width parameter min. 80 40 40 limits max. ns ns ns unit f(f sys ) 20 mhz
94 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c(ta) t su(ta jin -ta jout ) t su(ta jout -ta jin ) symbol parameter min. 800 200 200 limits max. ns ns ns unit timer a input (two-phase pulse input in event counter mode) taj in input cycle time taj in input setup time taj out input setup time t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t h(t in -up) t su(up-t in ) t su(taj in -taj out ) t su(taj out -taj in ) t su(taj in -taj out ) t su(taj out -taj in ) t c(ta) ?gating input in timer mode ?count input in event counter mode ?external trigger input in one-shot pulse mode ?external trigger input in pulse width modulation mode tai in input tai out input (up-down input) tai out input (up-down input) ?up-down and count input in event counter mode tai in input (when count by falling) tai in input (when count by rising) taj in input taj out input ?two-phase pulse input in event counter mode test conditions ?v cc = 5 v 0.5 v, ta = ?0 to 85 c ?input timing voltage : v il = 1.0 v, vih = 4.0 v
95 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz f(f sys ) 20 mhz t c(tb) t w(tbh) t w(tbl) t c(tb) t w(tbh) t w(tbl) timer b input (count input in event counter mode) symbol tbi in input cycle time (one edge count) tbi in input high-level pulse width (one edge count) tbi in input low-level pulse width (one edge count) tbi in input cycle time (both edge count) tbi in input high-level pulse width (both edge count) tbi in input low-level pulse width (both edge count) parameter limits min. 80 40 40 160 80 80 max. ns ns ns ns ns ns unit limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse period measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. limits symbol parameter min. max. unit 16 10 9 f(f sys ) 8 10 9 f(f sys ) 8 10 9 f(f sys ) (800) (400) (400) t c(tb) t w(tbh) t w(tbl) tbi in input cycle time tbi in input high-level pulse width tbi in input low-level pulse width ns ns ns timer b input (pulse width measurement mode) note: the tbi in input cycle time requires 4 or more cycles of a count source. the tbi in input high-level pulse width and the tbi in input low-level pulse width respectively require 2 or more cycles of a count source. the limits in this table are applied when the count source = f 2 at f(f sys ) 20 mhz. t c(ck) t w(ckh) t w(ckl) t d(c-q) t h(c-q) t su(d-c) t h(c-d) serial i/o symbol clk i input cycle time clk i input high-level pulse width clk i input low-level pulse width t x d i output delay time t x d i hold time r x d i input setup time r x d i input hold time parameter limits min. 200 100 100 0 20 90 max. 80 ns ns ns ns ns ns ns unit
96 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t w(inh) t w(inl) symbol int i input high-level pulse width int i input low-level pulse width parameter min. 250 250 limits max. ns ns unit external interrupt (int i ) input t c(tb) t w(tbh) t w(tbl) t su(d-c) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c-q) t h(c-d) t h(c-q) tbi in input int i input clk i input txd i output rxd i input test conditions vcc = 5 v 20 to 85 input timing voltage : v il = 1.0 v, v ih = 4.0 v output timing voltage : v ol = 0.8 v, v oh = 2.0 v, c l = 50 pf
97 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers t c t w(half) t w(h) t w(l) t r t f max. 0.55 tc 8 8 min. 50 0.45 tc 0.5 t c ?8 0.5 t c ?8 external clock input cycle time external clock input pulse width with half input-voltage external clock input high-level pulse width external clock input low-level pulse width external clock input rise time external clock input fall time limits external clock input symbol parameter ns ns ns ns ns ns unit external clock input t r t f t w(l) t w(h) t w(half) x in t c test conditions vcc = 5 v 20 to 85 input timing voltage : v il = 1.0 v, v ih = 4.0 v (t w(h) , t w(l) , t r , t f ) output timing voltage : 2.5 v ( t c , t w(half) ) timing requirements (v cc = 5 v?.5 v, v ss = 0 v, t a = ?0 to 85 ?, f(x in ) = 20 mhz, unless otherwise noted)
98 m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. some parametric limits are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers package outline qfp64-p-1414-0.80 1.11 weight(g) jedec code eiaj package code lead material alloy 42 64p6n-a plastic 64pin 14 14mm body qfp symbol min nom max a a 2 b c d e h e l l 1 y b 2 dimension in millimeters h d a 1 0.2 0.1 0.5 i 2 1.3 m d 14.6 m e 14.6 10 0.2 b x m 64 33 32 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d sdip64-p-750-1.78 weight(g) 7.9 jedec code eiaj package code lead material alloy 42/cu alloy 64p4b plastic 64pin 750mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.38 3.8 0.4 0.5 0.59 0.9 1.0 1.3 0.65 0.75 1.05 0.2 0.25 0.32 56.2 56.4 56.6 16.85 17.0 17.15 1.778 19.05 2.8 0 15 5.08 e e 1 mmp
m37905m4c-xxxfp, m37905m4c-xxxsp m37905m6c-xxxfp, M37905M6C-XXXSP m37905m8c-xxxfp, m37905m8c-xxxsp preliminar y notice: this is not a final specification. som e param etric lim its are subject to change. 16-bit cmos microcomputer mitsubishi microcomputers notes regarding these materials these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product b est suited to the customer? application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party? rights, origina ting in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommen ded that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assu mes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubish i semiconductor home page (http://www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibilit y for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used und er circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a pro duct contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these m aterials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a licen se from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is pro hibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further detai ls on these materials or the products contained therein. ?2001 mitsubishi electric corp. new publication, effective jul., 2001. specifications subject to change without notice. keep safety first in your circuit designs! mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making y our circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
2.0 1. revised points 010301 refer to ?orrections and supplementary explanation for m37905mxc-xxxfp/sp datasheet (rev.a) . 2. added sections block diagram, basic function blocks, memory, central processing unit (cpu), bus interface unit, processor modes, interrupts, timer, timer fun- ction for motor control, pulse output port mode 0/1, serial i/o ports, a-d converter, d-a converter, watchdog timer, input/output pins, reset circuit, oscillation circuit, clock generating circuit, standby function, power saving function, debug function, electrical characteristics, pa- ckage outline 3.0 refer to corrections and explanation for m37905mxc-xxxfp/sp datasheet (rev.b) . 010702 note : represents the new information added in rev.3.0. rev. rev. no. date 1.0 first edition. the following are released. 000630 ?description revision history m37905mxc-xxxfp/sp datasheet (1/1) revision description
corrections and supplementary explanation for m37905mxc-xxxfp/sp datasheet (rev.b) no.1 page page 1, distinctive features page 1, application page 1, m37905mxc-xxxfp pin configura- tion (top view) page 2, m37905mxc-xxxsp pin configura- tion (top view) page 4, item 1 item 2 item 3: clock gen- erating circuit item 4: power dis- sipation error 8-bit a-d converter control devices for equipment required for motor control such as inverter ? pin no.23 ; p5 3 /int 3 /rtp trg0 /x cout pin no.24; p5 2 /int 2 /rtp trg1 /x cin pin no.50; p1 1 /cts 0 /clk 0 pin no.28; x ont pin no.31; p5 3 /int 3 /rtp trg0 /x cout pin no.32; p5 2 /int 2 /rtp trg1 /x cin external main-clock input frequency f(x in ) system clock input frequency f(f sys ) 2 circuits incorporated (at f(x in ) = 20 mhz, ) correction 8-bit d-a converter control devices for equipment, requiring motor control, such as inverter pin no.23; p5 3 /int 3 /rtp trg0 pin no.24; p5 2 /int 2 /rtp trg1 pin no.50; p1 1 /cts 0 /clk 0 pin no.28; x out pin no.31; p5 3 /int 3 /rtp trg0 pin no.32; p5 2 /int 2 /rtp trg1 external clock input frequency f(x in ) ? external sub-clock input frequency f(x cin ) is deleted. system clock frequency f(f sys ) incorporated (at f(f sys ) = 20 mhz, ) (1/2) page 43, figure 43 2 5 position-data-retain function control register retained trigger s polarity select bit 0 1 3 4 2 5 position-data-retain function control register retain-trigger polarity select bit 0 1 3 4 page 70, figure 79 3: , it is necessary to wait for 1 s or more before 3: , it is necessary to wait for 1 s or more before page 78, figure 88 comparison result register 0 (de 16 ) comparison result register 1 (df 16 ) comparator result register 0 (de 16 ) comparator result register 1 (df 16 ) page 81, left column line 7 right column lines 5, 10, 21 the clock control register the clock control register 0 page 90, recommended operating conditions min. limits max. symbol parameter unit typ. 0 v il low-level input voltage 0.2 v cc vma min. limits max. symbol parameter unit typ. 0 v il low-level input voltage 0.2 v cc v page 91, dc electrical characteristics (v cc = 5v, , f(f sys ) = 20 m hz) (v cc = 5v, , f(f sys ) = 20 mhz, unless otherwise noted)
corrections and supplementary explanation for m37905mxc-xxxfp/sp datasheet (rev.b) no.2 page error correction (2/2) min. limits max. symbol parameter unit typ. 2 v ol v p1 0 -p1 7 , , p7 0 p7 4 , low-level output voltage min. limits max. symbol parameter unit typ. 2 v ol v p1 0 -p1 7 , , p7 0 p7 7 , low-level output voltage min. limits max. symbol parameter unit typ. 2 v ol v rom hold voltage test conditions 50 min. limits max. symbol parameter unit typ. 2 v ol v rom hold voltage test conditions min. limits max. symbol parameter unit typ. 25 i cc ma power source current test conditions 50 f(f sys ) = 20 mhz. min. limits max. symbol parameter unit typ. 25 i cc ma power source current test conditions f(f sys ) = 20 mhz. output- only pins output- only pins when clock when clock page 91, dc electrical characteristics

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